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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-01-05 16:57:29 -06:00
commit fb3207fc72
23 changed files with 4386 additions and 2282 deletions
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4
bin/elf2hex.sh
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@ -6,12 +6,12 @@
for file in work/rv64i_m/*/*.elf ; do
memfile=${file%.elf}.elf.memfile
echo riscv64-unknown-elf-elf2hex --bit-width 64 --input "$file" --output "$memfile"
echo riscv64-unknown-elf-elf2hex --bit-width 64 --input "$file"
riscv64-unknown-elf-elf2hex --bit-width 64 --input "$file" --output "$memfile"
done
for file in work/rv32i_m/*/*.elf ; do
memfile=${file%.elf}.elf.memfile
echo riscv64-unknown-elf-elf2hex --bit-width 32 --input "$file" --output "$memfile"
echo riscv64-unknown-elf-elf2hex --bit-width 32 --input "$file"
riscv64-unknown-elf-elf2hex --bit-width 32 --input "$file" --output "$memfile"
done

0
bin/exe2memfile.pl → bin/exe2memfile-deleteme.pl
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193
pipelined/bin/exe2memfile0.pl
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@ -1,193 +0,0 @@
#!/usr/bin/perl -w
# exe2memfile.pl
# David_Harris@hmc.edu 26 November 2020
# Converts an executable file to a series of 32-bit hex instructions
# to read into a Verilog simulation with $readmemh
use File::stat;
use IO::Handle;
if ($#ARGV == -1) {
die("Usage: $0 executable_file");
}
# array to hold contents of memory file
my @memfilebytes = (0)*16384*4;
my $maxaddress = 0;
STDOUT->autoflush(1);
# *** Ross Thompson I think there is a bug here needs to be +1
print ("Processing $#ARGV memfiles: \n");
my $frac = $#ARGV/10;
for(my $i=0; $i<=$#ARGV; $i++) {
if ($i < 10 || $i % $frac == 0) { print ("$i ") };
my $fname = $ARGV[$i];
# print "fname = $fname";
my $ofile = $fname.".objdump";
my $memfile = $fname.".memfile";
my $needsprocessing = 0;
if (!-e $memfile) { $needsprocessing = 1; } # create memfile if it doesn't exist
else {
my $osb = stat($ofile) || die("Can't stat $ofile");
my $msb = stat($memfile) || die("Can't stat $memfile");
my $otime = $osb->mtime;
my $mtime = $msb->mtime;
if ($otime > $mtime) { $needsprocessing = 1; } # is memfile out of date?
}
if ($needsprocessing == 1) {
open(FILE, $ofile) || die("Can't read $ofile");
my $mode = 0; # parse for code
my $section = "";
my $data = "";
my $address;
my $first = 0;
my $firstAddress;
# initialize to all zeros;
# *** need to fix the zeroing range. Not always 64K
for (my $i=0; $i < 65536*4; $i++) {
$memfilebytes[$i] = "00";
}
while(<FILE>) {
# objdump fill is divided into several .sections of which only some we want to actually process.
# In general we want everything except the .comment and .*attributes
if (/Disassembly of section (.*):/) {
$section = $1;
print ("setting section to $section\n");
} else {
# now check if the section is one we are interested in processing.
#if ($section ne ".comment" && $section ne ".riscv.attributes" && $section =~ /\.debug.*/) {
if ($section =~ "\.init|\.text|\..*data|\..*bss") {
# the structure is: possible space(s) hex number: possible space(s) hex number space(s) junk
# there are also lines we need to skip: possible space(s) hex number <string>:
if (/^\s*([0-9A-Fa-f]{1,16}):\s+([0-9A-Fa-f]+).*$/) {
$address = &fixadr($1);
if ($first == 0) {
$first = 1;
$firstAddress = $address;
}
$data = $2;
&emitData($address, $data);
# my $len = length($data);
# for (my $i=0; $i<$len/2; $i++) {
# $memfilebytes[$address+$i] = substr($data, $len-2-2*$i, 2);
# }
# print ("Addr $address $data\n");
# } elsif (/^\s*\.\.\./) {
# print ("Got ...\n");
# } else {
# print ("No match\n");
}
}
}
# # *** this mode stuff does not work if a section is missing or reordered.
# if ($mode == 0) { # Parse code
# # print("Examining $_\n");
# if (/^\s*(\S{1,16}):\s+(\S+)\s+/) {
# $address = &fixadr($1);
# my $instr = $2;
# my $len = length($instr);
# for (my $i=0; $i<$len/2; $i++) {
# $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
# }
# print ("address $address $instr\n");
# }
# if (/Disassembly of section .data:/) { $mode = 1;}
# } elsif ($mode == 1) { # Parse data segment
# if (/^\s*(\S{1,16}):\s+(.*)/) {
# $address = &fixadr($1);
# # print "addresss $address maxaddress $maxaddress\n";
# if ($address > $maxaddress) { $maxaddress = $address; }
# my $line = $2;
# # merge chunks with spaces
# # *** might need to change
# $line =~ s/(\S)\s(\S)/$1$2/g;
# # strip off comments
# $line =~ /^(\S*)/;
# $payload = $1;
# &emitData($address, $payload);
# }
# if (/Disassembly of section .comment:/) { $mode = 2; }
# } elsif ($mode == 2) { # parse the comment section
# if (/Disassembly of section .riscv.attributes:/) { $mode = 3; }
# }
}
close(FILE);
$maxaddress = $address + 32; # pad some zeros at the end
# print to memory file
# *** this is a problem
if ($fname =~ /rv32/) {
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 4) {
for ($j=3; $j>=0; $j--) {
no warnings 'uninitialized';
my $value = $memfilebytes[$i+$j];
if ($value eq ""){
print MEMFILE "00";
} else {
print MEMFILE "$memfilebytes[$i+$j]";
}
}
print MEMFILE "\n";
}
close(MEMFILE);
} else {
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 8) {
for ($j=7; $j>=0; $j--) {
no warnings 'uninitialized';
my $value = $memfilebytes[$i+$j];
if ($value eq ""){
print MEMFILE "00";
} else {
print MEMFILE "$memfilebytes[$i+$j]";
}
}
print MEMFILE "\n";
}
close(MEMFILE);
}
}
}
print("\n");
sub emitData {
# print the data portion of the ELF into a memroy file, including 0s for empty stuff
# deal with endianness
my $address = shift;
my $payload = shift;
# print("Emitting data. address = $address payload = $payload\n");
my $len = length($payload);
if ($len <= 8) {
# print word or halfword
for(my $i=0; $i<$len/2; $i++) {
my $adr = $address+$i;
my $b = substr($payload, $len-2-2*$i, 2);
$memfilebytes[$adr] = $b;
# print(" $adr $b\n");
}
} elsif ($len == 12) {
# weird case of three halfwords on line
&emitData($address, substr($payload, 0, 4));
&emitData($address+2, substr($payload, 4, 4));
&emitData($address+4, substr($payload, 8, 4));
} else {
&emitData($address, substr($payload, 0, 8));
&emitData($address+4, substr($payload, 8, $len-8));
}
}
sub fixadr {
# strip off leading 8 from address and convert to decimal
# if the leading 8 is not present don't remove.
my $adr = shift;
#print "addr $adr\n";
return hex($adr);
}

18
pipelined/regression/Makefile
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@ -1,18 +1,26 @@
make clean:
make clean -C ../../addins/riscv-arch-test
make clean -C ../../tests/wally-riscv-arch-test
make all:
# Build riscv-arch-test 64 and 32-bit versions
make -C ../../addins/riscv-arch-test
make -C ../../addins/riscv-arch-test XLEN=32
exe2memfile.pl ../../addins/riscv-arch-test/work/*/*/*.elf
cd ../../addins/riscv-arch-test; elf2hex.sh
# extractFunctionRadix. ***
# Build wally-riscv-arch-test
make -C ../../tests/wally-riscv-arch-test/
make -C ../../tests/wally-riscv-arch-test/ XLEN=32
exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
cd ../../tests/wally-riscv-arch-test; elf2hex.sh
# ***extractFunctionRadix
# *** use elf2hex
# *** add optional imperas tests
# Only compile Imperas tests if they are installed
# make -C ../../addins/imperas-riscv-tests
# make -C ../../addins/imperas-riscv-tests XLEN=64
# cd ../../addins/imperas-riscv-tests; elf2hex.sh
# Link Linux test vectors (fix this later***)
#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

2
pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<!
do wally-pipelined-batch.do rv32gc wally32priv
do wally-pipelined-batch.do rv64gc arch64d
!

6
pipelined/src/uncore/plic.sv
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@ -187,11 +187,11 @@ module plic (
| ({N{pendingMaxP[2]}} & pendingArray[2])
| ({N{pendingMaxP[1]}} & pendingArray[1]);
// find the lowest ID amongst active interrupts at the highest priority
int k; // *** rewrite as priority encoder
logic [5:0] k;
always_comb begin
intClaim = 6'b0;
for(k=N; k>0; k=k-1) begin
if(pendingRequestsAtMaxP[k]) intClaim = k[5:0];
for (k=N; k>0; k=k-1) begin
if (pendingRequestsAtMaxP[k]) intClaim = k;
end
end

60
pipelined/testbench/tests.vh
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@ -1049,7 +1049,7 @@ string imperas32f[] = '{
`RISCVARCHTEST,
"rv64i_m/D/d_fadd_b10-01", "8690",
"rv64i_m/D/d_fadd_b1-01", "8430",
// "rv64i_m/D/d_fadd_b11-01", "74da0", //memfile
"rv64i_m/D/d_fadd_b11-01", "74da0",
"rv64i_m/D/d_fadd_b12-01", "2350",
"rv64i_m/D/d_fadd_b13-01", "3cb0",
"rv64i_m/D/d_fadd_b2-01", "5160",
@ -1073,11 +1073,11 @@ string imperas32f[] = '{
"rv64i_m/D/d_fcvt.d.w_b25-01", "2120",
"rv64i_m/D/d_fcvt.d.w_b26-01", "2220",
"rv64i_m/D/d_fcvt.d.wu_b25-01", "2110",
// "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", //memfile
"rv64i_m/D/d_fcvt.d.wu_b26-01", "2220",
"rv64i_m/D/d_fcvt.l.d_b1-01", "2120",
"rv64i_m/D/d_fcvt.l.d_b22-01", "2260",
"rv64i_m/D/d_fcvt.l.d_b23-01", "2180",
// "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", // memfile
"rv64i_m/D/d_fcvt.l.d_b24-01", "2360",
"rv64i_m/D/d_fcvt.l.d_b27-01", "2110",
"rv64i_m/D/d_fcvt.l.d_b28-01", "2120",
"rv64i_m/D/d_fcvt.l.d_b29-01", "22a0",
@ -1095,17 +1095,17 @@ string imperas32f[] = '{
"rv64i_m/D/d_fcvt.s.d_b27-01", "2110",
"rv64i_m/D/d_fcvt.s.d_b28-01", "2110",
"rv64i_m/D/d_fcvt.s.d_b29-01", "22a0",
// "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", // memfile
// "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", // memfile
"rv64i_m/D/d_fcvt.w.d_b1-01", "2120",
"rv64i_m/D/d_fcvt.w.d_b22-01", "2160",
"rv64i_m/D/d_fcvt.w.d_b23-01", "2180",
"rv64i_m/D/d_fcvt.w.d_b24-01", "2360",
"rv64i_m/D/d_fcvt.w.d_b27-01", "2120",
"rv64i_m/D/d_fcvt.w.d_b28-01", "2120",
"rv64i_m/D/d_fcvt.w.d_b29-01", "22a0",
// "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", // memfile
"rv64i_m/D/d_fcvt.wu.d_b1-01", "2120",
"rv64i_m/D/d_fcvt.wu.d_b22-01", "2160",
"rv64i_m/D/d_fcvt.wu.d_b23-01", "2180",
// "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", // memfile
"rv64i_m/D/d_fcvt.wu.d_b24-01", "2360",
"rv64i_m/D/d_fcvt.wu.d_b27-01", "2120",
"rv64i_m/D/d_fcvt.wu.d_b28-01", "2120",
"rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0",
@ -1119,7 +1119,7 @@ string imperas32f[] = '{
// "rv64i_m/D/d_fdiv_b6-01", "38f0", // flags
"rv64i_m/D/d_fdiv_b7-01", "5530",
// "rv64i_m/D/d_fdiv_b8-01", "11c10", // flags
// "rv64i_m/D/d_fdiv_b9-01", "1b0f0", // memfile might be a flag too
// "rv64i_m/D/d_fdiv_b9-01", "1b0f0", might be a flag too
"rv64i_m/D/d_feq_b1-01", "7430",
"rv64i_m/D/d_feq_b19-01", "c4c0",
"rv64i_m/D/d_fld-align-01", "2010",
@ -1129,8 +1129,8 @@ string imperas32f[] = '{
"rv64i_m/D/d_flt_b19-01", "d800",
"rv64i_m/D/d_fmadd_b14-01", "3fd0",
"rv64i_m/D/d_fmadd_b16-01", "43b0",
// "rv64i_m/D/d_fmadd_b17-01", "43b0", //memfile
// "rv64i_m/D/d_fmadd_b18-01", "5a20", // memfile
"rv64i_m/D/d_fmadd_b17-01", "43b0",
"rv64i_m/D/d_fmadd_b18-01", "5a20",
"rv64i_m/D/d_fmadd_b2-01", "5ab0",
"rv64i_m/D/d_fmadd_b3-01", "119d0",
"rv64i_m/D/d_fmadd_b4-01", "3df0",
@ -1143,9 +1143,9 @@ string imperas32f[] = '{
"rv64i_m/D/d_fmin_b1-01", "8430",
"rv64i_m/D/d_fmin_b19-01", "d4b0",
"rv64i_m/D/d_fmsub_b14-01", "3fd0",
// "rv64i_m/D/d_fmsub_b16-01", "43b0", // memfile
// "rv64i_m/D/d_fmsub_b17-01", "43b0",
// "rv64i_m/D/d_fmsub_b18-01", "5a20", // memfile
"rv64i_m/D/d_fmsub_b16-01", "43b0",
"rv64i_m/D/d_fmsub_b17-01", "43b0",
"rv64i_m/D/d_fmsub_b18-01", "5a20",
"rv64i_m/D/d_fmsub_b2-01", "5ab0",
"rv64i_m/D/d_fmsub_b3-01", "119f0",
"rv64i_m/D/d_fmsub_b4-01", "3df0",
@ -1174,9 +1174,9 @@ string imperas32f[] = '{
"rv64i_m/D/d_fnmadd_b14-01", "3fd0",
"rv64i_m/D/d_fnmadd_b16-01", "4390",
"rv64i_m/D/d_fnmadd_b17-01", "4390",
// "rv64i_m/D/d_fnmadd_b18-01", "5a20", // memfile
"rv64i_m/D/d_fnmadd_b18-01", "5a20",
"rv64i_m/D/d_fnmadd_b2-01", "5ab0",
// "rv64i_m/D/d_fnmadd_b3-01", "119d0", // memfile
"rv64i_m/D/d_fnmadd_b3-01", "119d0",
"rv64i_m/D/d_fnmadd_b4-01", "3df0",
"rv64i_m/D/d_fnmadd_b5-01", "4480",
"rv64i_m/D/d_fnmadd_b6-01", "3df0",
@ -1184,15 +1184,15 @@ string imperas32f[] = '{
"rv64i_m/D/d_fnmadd_b8-01", "15aa0",
"rv64i_m/D/d_fnmsub_b14-01", "3fd0",
"rv64i_m/D/d_fnmsub_b16-01", "4390",
// "rv64i_m/D/d_fnmsub_b17-01", "4390", // memfile - there's a "it" in the file
// "rv64i_m/D/d_fnmsub_b18-01", "5a20", // memfile
"rv64i_m/D/d_fnmsub_b17-01", "4390",
"rv64i_m/D/d_fnmsub_b18-01", "5a20",
"rv64i_m/D/d_fnmsub_b2-01", "5aa0",
"rv64i_m/D/d_fnmsub_b3-01", "119d0",
"rv64i_m/D/d_fnmsub_b4-01", "3e20",
"rv64i_m/D/d_fnmsub_b5-01", "4480",
"rv64i_m/D/d_fnmsub_b6-01", "3e10",
"rv64i_m/D/d_fnmsub_b7-01", "6050",
// "rv64i_m/D/d_fnmsub_b8-01", "15aa0", // memfile - not obvious have to check with .elf.debug
"rv64i_m/D/d_fnmsub_b8-01", "15aa0",
"rv64i_m/D/d_fsd-align-01", "2010",
"rv64i_m/D/d_fsgnj_b1-01", "8430",
"rv64i_m/D/d_fsgnjn_b1-01", "8430",
@ -1299,21 +1299,21 @@ string imperas32f[] = '{
"rv32i_m/F/fle_b1-01", "6220",
// "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
"rv32i_m/F/flt_b1-01", "6220",
// "rv32i_m/F/flt_b19-01", "8ee0", // memfile
"rv32i_m/F/flt_b19-01", "8ee0",
"rv32i_m/F/flw-align-01", "2010",
"rv32i_m/F/fmadd_b1-01", "96860",
"rv32i_m/F/fmadd_b14-01", "23d0",
// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30",
"rv32i_m/F/fmadd_b16-01", "39d0",
"rv32i_m/F/fmadd_b17-01", "39d0",
// "rv32i_m/F/fmadd_b18-01", "4d10", // memfile - incorrect last value - ln 4931 supposed to be 71bffff8
"rv32i_m/F/fmadd_b18-01", "4d10",
"rv32i_m/F/fmadd_b2-01", "4d60",
"rv32i_m/F/fmadd_b3-01", "d4f0",
"rv32i_m/F/fmadd_b4-01", "3700",
"rv32i_m/F/fmadd_b5-01", "3ac0",
"rv32i_m/F/fmadd_b6-01", "3700",
// "rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test
// "rv32i_m/F/fmadd_b8-01", "13f30", // memfile incorrect input - last test input Z
//"rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test; didn't run even with fixed memfile
"rv32i_m/F/fmadd_b8-01", "13f30",
"rv32i_m/F/fmax_b1-01", "7220",
"rv32i_m/F/fmax_b19-01", "9e00",
"rv32i_m/F/fmin_b1-01", "7220",
@ -1328,7 +1328,7 @@ string imperas32f[] = '{
"rv32i_m/F/fmsub_b3-01", "d4f0",
"rv32i_m/F/fmsub_b4-01", "3700",
"rv32i_m/F/fmsub_b5-01", "3ac0",
// "rv32i_m/F/fmsub_b6-01", "3700", // memfile
"rv32i_m/F/fmsub_b6-01", "3700",
"rv32i_m/F/fmsub_b7-01", "37f0",
"rv32i_m/F/fmsub_b8-01", "13f30",
"rv32i_m/F/fmul_b1-01", "7220",
@ -1336,7 +1336,7 @@ string imperas32f[] = '{
"rv32i_m/F/fmul_b3-01", "b320",
"rv32i_m/F/fmul_b4-01", "3480",
"rv32i_m/F/fmul_b5-01", "3700",
// "rv32i_m/F/fmul_b6-01", "3480", // memfile
"rv32i_m/F/fmul_b6-01", "3480",
"rv32i_m/F/fmul_b7-01", "3520",
"rv32i_m/F/fmul_b8-01", "104a0",
"rv32i_m/F/fmul_b9-01", "d960",
@ -1354,7 +1354,7 @@ string imperas32f[] = '{
// timeconsuming "rv32i_m/F/fnmadd_b15-01", "19bb40",
"rv32i_m/F/fnmadd_b16-01", "39d0",
"rv32i_m/F/fnmadd_b17-01", "39d0",
// "rv32i_m/F/fnmadd_b18-01", "4d10", // memfile
"rv32i_m/F/fnmadd_b18-01", "4d10",
"rv32i_m/F/fnmadd_b2-01", "4d60",
"rv32i_m/F/fnmadd_b3-01", "d4f0",
"rv32i_m/F/fnmadd_b4-01", "3700",
@ -1363,17 +1363,17 @@ string imperas32f[] = '{
"rv32i_m/F/fnmadd_b7-01", "37f0",
"rv32i_m/F/fnmadd_b8-01", "13f30",
"rv32i_m/F/fnmsub_b1-01", "96870",
// "rv32i_m/F/fnmsub_b14-01", "23d0", // memfile
"rv32i_m/F/fnmsub_b14-01", "23d0",
// timeconsuming "rv32i_m/F/fnmsub_b15-01", "19bb30",
"rv32i_m/F/fnmsub_b16-01", "39d0",
"rv32i_m/F/fnmsub_b17-01", "39d0",
// "rv32i_m/F/fnmsub_b18-01", "4d10", // memfile
"rv32i_m/F/fnmsub_b18-01", "4d10",
"rv32i_m/F/fnmsub_b2-01", "4d60",
// "rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
//"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
"rv32i_m/F/fnmsub_b4-01", "3700",
"rv32i_m/F/fnmsub_b5-01", "3ac0",
"rv32i_m/F/fnmsub_b6-01", "3700",
// "rv32i_m/F/fnmsub_b7-01", "37f0", // memfile last input merged with a deadbeef
"rv32i_m/F/fnmsub_b7-01", "37f0",
"rv32i_m/F/fnmsub_b8-01", "13f30",
"rv32i_m/F/fsgnj_b1-01", "7220",
"rv32i_m/F/fsgnjn_b1-01", "7220",
@ -1396,7 +1396,7 @@ string imperas32f[] = '{
"rv32i_m/F/fsub_b3-01", "b320",
"rv32i_m/F/fsub_b4-01", "3480",
"rv32i_m/F/fsub_b5-01", "3700",
// "rv32i_m/F/fsub_b7-01", "3520", // memfile
"rv32i_m/F/fsub_b7-01", "3520",
"rv32i_m/F/fsub_b8-01", "104a0",
"rv32i_m/F/fsw-align-01", "2010"
};

4
tests/wally-riscv-arch-test/Makefile
View File

@ -59,7 +59,7 @@ endif
default: $(DEFAULT_TARGET)
variant: simulate verify
variant: compile simulate verify
all_variant:
@for isa in $(RISCV_ISA_ALL); do \
@ -87,7 +87,7 @@ simulate:
run -C $(SUITEDIR)
verify: simulate
# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
postverify:
ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)

23
tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include
View File

@ -4,12 +4,14 @@
act_dir := .
src_dir := $(act_dir)/src
ref_dir := $(act_dir)/references
work_dir := $(WORK)
work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE)
include $(act_dir)/Makefrag
ifneq ($(RISCV_TEST),)
target_tests = $(RISCV_TEST).elf
target_tests_nosim = $(empty)
endif
default: all
@ -46,10 +48,27 @@ $(work_dir_isa)/%.elf: $(src_dir)/%.S
endef
target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
target_elf_nosim = $(foreach e,$(addsuffix .elf, $(target_tests_nosim)),$(work_dir_isa)/$(e))
combined_elf = $(target_elf_nosim) $(target_elf)
target_log = $(patsubst %.elf,%.log,$(target_elf))
compile: $(target_elf)
run: $(target_log)
ifdef target_tests_nosim
compile: copy
# now copy must be performed before compile,
# allowing us to copy over outputs if they won't simulate on spike correctly.
endif
copy:
@mkdir -p $(work_dir_isa)
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
$(V) echo "Copying References without simulating"
$(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done
compile: $(combined_elf)
run: $(target_log)
# note that run doesnt use the combined elf so it doesnt run the nosim tests.
#------------------------------------------------------------
# Clean up

680
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output Normal file
View File

@ -0,0 +1,680 @@
00000000
00000000
00000000
00000000
00000000
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
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00000000

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
View File

@ -30,7 +30,8 @@
rv32i_sc_tests = \
WALLY-MMU-SV32 \
WALLY-PMP
# WALLY-PMA \
target_tests_nosim = WALLY-PMA \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output
View File

@ -5,6 +5,8 @@ beef0077
beef0099
beef0440
beef0bb0
11100393
00008067
beef0055
beef0099
0000000d
@ -14,7 +16,7 @@ beef0099
00000bad
0000000d
00000bad
000e600d
00000111
00000009
0000000d
00000bad
@ -1020,5 +1022,3 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

1970
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output
View File

File diff suppressed because it is too large Load Diff

22
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMP.reference_output
View File

@ -1,10 +1,19 @@
0fffffff
20040000
2004003f
20040080
20040084
200400c0
2004013f
2fffffff
0009001f
0018900c
1f000000
0018900c
200400c0
00000005
00000bad
00600dBB
00600dbb
0000000b
00600d15
00600d02
@ -16,6 +25,7 @@
00000bad
00000001
00000bad
00000111
00000009
deadbeef
deadbeef
@ -1012,13 +1022,3 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S
View File

@ -73,8 +73,6 @@
.4byte 0x80803AA0, 0xBEEF0BB0, 0x0 # 12.3.1.3.7
.4byte 0x8000FFA0, 0x11100393, 0x0 # write executable code for "li x7, 0x111; ret" to executable region.
.4byte 0x8000FFA4, 0x00008067, 0x0 # Used for 12.3.1.3.1, 12.3.1.3.2
.4byte 0x80801DE0, 0x11100393, 0x0 # write executable code for "li x7, 0x111; ret" to NON-executable region.
.4byte 0x80801DE4, 0x00008067, 0x0 # Used for 12.3.1.3.5
# test 12.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
.4byte 0x0, 0x0, 0x4 # satp.MODE = baremetal / no translation.
@ -87,8 +85,6 @@
.4byte 0x80803AA0, 0xBEEF0BB0, 0x1
.4byte 0x8000FFA0, 0x11100393, 0x1
.4byte 0x8000FFA4, 0x00008067, 0x1
.4byte 0x80801DE0, 0x11100393, 0x1
.4byte 0x80801DE4, 0x00008067, 0x1
# test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
.4byte 0x0, 0x0, 0x5 # satp.MODE = sv32, Nothing written to output

116
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
View File

@ -2,7 +2,7 @@
//
// WALLY-PMA
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu> (Copied heavily from SV48 test).
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2021-06-15
//
@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.S"
// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
// Ideally this should mean that a test can be written by simply adding .8byte statements as below.
// Ideally this should mean that a test can be written by simply adding .4byte statements as below.
# ---------------------------------------------------------------------------------------------
# Test Contents
@ -31,36 +31,108 @@
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.8byte [x28 Value], [x29 Value], [x30 value]'
# '.4byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.8byte [address], [value], [test type]'
# '.4byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler
#
# ---------------------------------------------------------------------------------------------
# =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
# Tests memory load, store, and /* *** execute? */ permissions based on table 12.3 in the *** riscv book, copied below
# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
# Test 12.3.2.1.1 check enabled devices
# | Region | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
.8byte 0x1000, 0x0, 0xB # | ROM | Any | YES | NO | YES | YES | NO | NO | # *** Impossible to write? how am I supposed to put a known value in ROM to read out?
.8byte 0x2000000, 0x0, 0xB # | CLINT | Any | YES | YES | NO | NO | NO | NO |
.8byte 0xC000000, 0x0, 0xB # | PLIC | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x10000000, 0x0, 0xB # | UART0 | 8-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x20000000, 0x0, 0xB # | GPIO | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x800F0000, 0x0, 0xB # | DRAM | Any | YES | YES | YES | YES | YES | YES |
# *** the dram one has a little offset so we don't accidentally write over the code of this test.
# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO |
# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO |
# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
# Test 12.3.2.1.2 Check Regions with no enabled device fail all
.8byte 0x0000, 0x0, 0xC
.8byte 0x3000, 0x0, 0xC
.8byte 0x4000000, 0x0, 0xC
.8byte 0xE0000000, 0x0, 0xC
.8byte 0x12000000, 0x0, 0xC
.8byte 0xA0000000, 0x0, 0xC
# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
.8byte 0x0, 0x0, 0x3 // terminate tests
# ----------------- ROM ---------------------
# *** the rom is read only and these read tests depend on reading a known value out of memory.
# Is there some guaranteed value that I can read out of the ROM
# otherwise the read test can be modified to just check that the read happened,
# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
# .4byte 0x1000, 0xBEEF0001, 0x0 # 32-bit write: store access fault
# .4byte 0x1000, 0xBEEF0001, 0x1 # 32-bit read: success
# .4byte 0x1000, 0xBEEF0002, 0x12 # 16-bit write: store access fault
# .4byte 0x1000, 0xBEEF0002, 0x15 # 16-bit read: success
# .4byte 0x1000, 0xBEEF0003, 0x13 # 08-bit write: store access fault
# .4byte 0x1000, 0xBEEF0003, 0x16 # 08-bit read: success
# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
# .4byte 0x1000, 0x111, 0x2 # execute: success
# ----------------- CLINT ---------------------
.4byte 0x2000000, 0xBEEF00B5, 0x0 # 32-bit write: success
.4byte 0x2000000, 0xBEEF00B5, 0x1 # 32-bit read: success
.4byte 0x2000000, 0xBEEF00B6, 0x12 # 16-bit write: success
.4byte 0x2000000, 0xBEEF00B6, 0x15 # 16-bit read: success
.4byte 0x2000000, 0xBEEF00B7, 0x13 # 08-bit write: success
.4byte 0x2000000, 0xBEEF00B7, 0x16 # 08-bit read: success
.4byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- PLIC ---------------------
.4byte 0xC000000, 0xBEEF00B9, 0x0 # 32-bit write: success
.4byte 0xC000000, 0xBEEF00B9, 0x1 # 32-bit read: success
.4byte 0xC000000, 0xBEEF00BA, 0x12 # 16-bit write: store access fault
.4byte 0xC000000, 0xBEEF00BA, 0x15 # 16-bit read: load access fault
.4byte 0xC000000, 0xBEEF00BB, 0x13 # 08-bit write: store access fault
.4byte 0xC000000, 0xBEEF00BB, 0x16 # 08-bit read: load access fault
.4byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- UART0 ---------------------
.4byte 0x10000000, 0xBEEF00BD, 0x0 # 32-bit write: store access fault
.4byte 0x10000000, 0xBEEF00BD, 0x1 # 32-bit read: load access fault
.4byte 0x10000000, 0xBEEF00BE, 0x12 # 16-bit write: store access fault
.4byte 0x10000000, 0xBEEF00BE, 0x15 # 16-bit read: load access fault
.4byte 0x10000000, 0xBEEF00BF, 0x13 # 08-bit write: success
.4byte 0x10000000, 0xBEEF00BF, 0x16 # 08-bit read: success
.4byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- GPIO ---------------------
.4byte 0x1012000, 0xBEEF00C1, 0x0 # 32-bit write: success
.4byte 0x1012000, 0xBEEF00C1, 0x1 # 32-bit read: success
.4byte 0x1012000, 0xBEEF00C2, 0x12 # 16-bit write: store access fault
.4byte 0x1012000, 0xBEEF00C2, 0x15 # 16-bit read: load access fault
.4byte 0x1012000, 0xBEEF00C3, 0x13 # 08-bit write: store access fault
.4byte 0x1012000, 0xBEEF00C3, 0x16 # 08-bit read: load access fault
.4byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- DRAM ---------------------
# the following is already tested by the fact that this test runs without error:
# 32 bit reads and writes into DRAM,
# Execution in DRAM
# offset by 0xf000 to avoid overwriting the program
.4byte 0x8000F000, 0xBEEF00C5, 0x12 # 16-bit write: success
.4byte 0x8000F000, 0xBEEF00C5, 0x15 # 16-bit read: success
.4byte 0x8000F000, 0xBEEF00C6, 0x13 # 08-bit write: success
.4byte 0x8000F000, 0xBEEF00C6, 0x16 # 08-bit read: success
# ----------------- Inaccessible ---------------------
# show that load, store, and jalr cause faults in a region not defined by PMAs.
# *** should I go through every possible inaccessible region of memory or is one just fine?
.4byte 0xD000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault
.4byte 0xD000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault
.4byte 0x1000, 0x111, 0x2 # execute: instruction access fault
.4byte 0x0, 0x0, 0x3 // terminate tests

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S
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@ -44,7 +44,7 @@
# Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below
# write pmpaddr regs. These should produce no outputs. *** consider replacing if a test needs to see the outputs of this.
# write pmpaddr regs
# | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments |
.4byte 0x0, 0x0FFFFFFF, 0xE # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW |
.4byte 0x1, 0x20040000, 0xE # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | |
@ -59,7 +59,7 @@
# write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output.
.4byte 0x0, 0x0009001F, 0xD # write pmpcfg0, output 0x0009001F
.4byte 0x1, 0x0018900C, 0xD # write pmpcfg1, output 0x0018900C
# .4byte 0x2, 0x00000000, 0xD # write pmpcfg2, output 0x00000000
# pmpcfg2 is zeroed out, so it doesn't need a write
.4byte 0x3, 0x1F000000, 0xD # write pmpcfg3, output 0x1F000000
# write known values to memory where W=0. This should be possible since we're in machine mode.

55
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.S
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@ -295,9 +295,17 @@ test_loop:
# x30 Value : Function : Fault output value : Normal output values
# ----------:---------------------------------------:------------------------:------------------------------------------------------
li x7, 0x0 # : : :
beq x30, x7, write_test # 0x0 : Write to address : 0xf : None
beq x30, x7, write32_test # 0x0 : Write 32 bits to address : 0xf : None
li x7, 0x12 # : : :
beq x30, x7, write16_test # 0x12 : Write 16 bits to address : 0xf : None
li x7, 0x13 # : : :
beq x30, x7, write08_test # 0x13 : Write 8 bits to address : 0xf : None
li x7, 0x1 # : : :
beq x30, x7, read_test # 0x1 : Read from address : 0xd, 0xbad : readvalue in hex
beq x30, x7, read32_test # 0x1 : Read 32 bits from address : 0xd, 0xbad : readvalue in hex
li x7, 0x15 # : : :
beq x30, x7, read16_test # 0x15 : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x16 # : : :
beq x30, x7, read08_test # 0x16 : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
li x7, 0x2 # : : :
beq x30, x7, executable_test # 0x2 : test executable at address : 0xc, 0xbad : leading 12 bits of the li instr written to address. In general this is 0x111. (be sure to also write a return instruction)
li x7, 0x3 # : : :
@ -311,7 +319,7 @@ test_loop:
li x7, 0xD # : : :
beq x30, x7, write_pmpcfg_0 # 0xD : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
li x7, 0xE # : : :
beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : None
beq x30, x7, write_pmpaddr_0 # 0xE : Write one of the pmpaddr csr's : None : readback of pmpaddr value
li x7, 0x8 # : : :
beq x30, x7, goto_m_mode # 0x8 : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
li x7, 0x9 # : : :
@ -321,20 +329,49 @@ test_loop:
# ------------------------------------------------------------------------------------------------------------------------------------
j terminate_test # default case: break
write_test:
# address to write in x28, value in x29
write32_test:
# address to write in x28, word value in x29
sw x29, 0(x28)
j test_loop # go to next test case
read_test:
# address to read in x28, expected value in x29 (unused, but there for your perusal).
write16_test:
# address to write in x28, halfword value in x29
sh x29, 0(x28)
j test_loop # go to next test case
write08_test:
# address to write in x28, value in x29
sb x29, 0(x28)
j test_loop # go to next test case
read32_test:
# address to read in x28, expected 32 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lw x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 4
addi x16, x16, 4
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
read16_test:
# address to read in x28, expected 16 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lh x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
read08_test:
# address to read in x28, expected 8 bit value in x29 (unused, but there for your perusal).
li x7, 0xBAD # bad value that will be overwritten on good reads.
lb x7, 0(x28)
sw x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
j test_loop # go to next test case
goto_s_mode:
li a0, 3 # Trap handler behavior (go to machine mode)
mv a1, x28 # return VPN

1360
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/PIPELINE.reference_output Normal file
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2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -31,8 +31,8 @@ rv64i_sc_tests = \
WALLY-MMU-SV39 \
WALLY-MMU-SV48 \
WALLY-PMP
# WALLY-PMA \
target_tests_nosim = WALLY-PMA \
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))

2002
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output
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14
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output
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@ -2,7 +2,7 @@
00000000
20040000
00000000
2004003F
2004003f
00000000
20040080
00000000
@ -46,6 +46,12 @@
00000000
00000bad
00000000
00000001
00000000
00000bad
00000000
00000111
00000000
00000009
00000000
deadbeef
@ -1016,9 +1022,3 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

120
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S
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@ -2,7 +2,7 @@
//
// WALLY-PMA
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu> (Copied heavily from SV48 test).
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2021-06-15
//
@ -40,25 +40,109 @@
# ---------------------------------------------------------------------------------------------
# =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
# Tests memory load, store, and /* *** execute? */ permissions based on table 12.3 in the *** riscv book, copied below
# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
# Test 12.3.2.1.1 check enabled devices
# | Region | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
.8byte 0x1000, 0x0, 0xB # | ROM | Any | YES | NO | YES | YES | NO | NO | # *** Impossible to write? how am I supposed to put a known value in ROM to read out?
.8byte 0x2000000, 0x0, 0xB # | CLINT | Any | YES | YES | NO | NO | NO | NO |
.8byte 0xC000000, 0x0, 0xB # | PLIC | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x10000000, 0x0, 0xB # | UART0 | 8-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x20000000, 0x0, 0xB # | GPIO | 32-bit | YES | YES | NO | NO | NO | NO |
.8byte 0x800F0000, 0x0, 0xB # | DRAM | Any | YES | YES | YES | YES | YES | YES |
# *** the dram one has a little offset so we don't accidentally write over the code of this test.
# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO |
# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO |
# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
# Test 12.3.2.1.2 Check Regions with no enabled device fail all
.8byte 0x0000, 0x0, 0xC
.8byte 0x3000, 0x0, 0xC
.8byte 0x4000000, 0x0, 0xC
.8byte 0xE0000000, 0x0, 0xC
.8byte 0x12000000, 0x0, 0xC
.8byte 0xA0000000, 0x0, 0xC
# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
# ----------------- ROM ---------------------
# *** the rom is read only and these read tests depend on reading a known value out of memory.
# Is there some guaranteed value that I can read out of the ROM
# otherwise the read test can be modified to just check that the read happened,
# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
# .8byte 0x1000, 0x0000DEADBEEF0000, 0x0 # 64-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0000, 0x1 # 64-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0001, 0x11 # 32-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0001, 0x14 # 32-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0002, 0x12 # 16-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0002, 0x15 # 16-bit read: success
# .8byte 0x1000, 0x0000DEADBEEF0003, 0x13 # 08-bit write: store access fault
# .8byte 0x1000, 0x0000DEADBEEF0003, 0x16 # 08-bit read: success
# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
# .8byte 0x1000, 0x111, 0x2 # execute: success
# ----------------- CLINT ---------------------
.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
.8byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- PLIC ---------------------
.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success
.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success
.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
.8byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- UART0 ---------------------
.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
.8byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- GPIO ---------------------
.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
.8byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
# ----------------- DRAM ---------------------
# the following is already tested by the fact that this test runs without error:
# 64 bit reads and writes into DRAM,
# Execution in DRAM
# offset by 0xf000 to avoid overwriting the program
.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x11 # 32-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x14 # 32-bit read: success
.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x12 # 16-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x15 # 16-bit read: success
.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x13 # 08-bit write: success
.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x16 # 08-bit read: success
# ----------------- Inaccessible ---------------------
# show that load, store, and jalr cause faults in a region not defined by PMAs.
# *** should I go through every possible inaccessible region of memory or is one just fine?
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
.8byte 0x1000, 0x111, 0x2 # execute: instruction access fault
.8byte 0x0, 0x0, 0x3 // terminate tests