forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
8225f85b86
@ -11,7 +11,6 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
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||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
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@ -157,37 +156,9 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
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||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextF
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||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/IfuBusFetch
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
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add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/IfuBusFetch
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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@ -205,194 +176,183 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
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add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
|
||||
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||
@ -473,8 +433,37 @@ add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine
|
||||
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfm/BusCurrState
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfm/LsuBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheFetchLine
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {9745 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
@ -490,4 +479,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {9530 ns} {9952 ns}
|
||||
WaveRestoreZoom {1238897 ns} {1239273 ns}
|
||||
|
||||
89
wally-pipelined/src/cache/icache.sv
vendored
89
wally-pipelined/src/cache/icache.sv
vendored
@ -28,28 +28,29 @@
|
||||
module icache
|
||||
(
|
||||
// Basic pipeline stuff
|
||||
input logic clk, reset,
|
||||
input logic CPUBusy,
|
||||
input logic [`PA_BITS-1:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
input logic clk, reset,
|
||||
input logic CPUBusy,
|
||||
input logic [`PA_BITS-1:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
input logic IgnoreRequest,
|
||||
|
||||
// Data read in from the ebu unit
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
(* mark_debug = "true" *) input logic ICacheBusAck,
|
||||
input logic [`ICACHE_BLOCKLENINBITS-1:0] ICacheMemWriteData,
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
(* mark_debug = "true" *) input logic ICacheBusAck,
|
||||
// Read requested from the ebu unit
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
|
||||
(* mark_debug = "true" *) output logic IfuBusFetch,
|
||||
// High if the instruction currently in the fetch stage is compressed
|
||||
output logic CompressedF,
|
||||
output logic CompressedF,
|
||||
// High if the icache is requesting a stall
|
||||
output logic ICacheStallF,
|
||||
input logic CacheableF,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
input logic InvalidateICacheM,
|
||||
output logic ICacheStallF,
|
||||
input logic CacheableF,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
input logic InvalidateICacheM,
|
||||
|
||||
// The raw (not decompressed) instruction that was requested
|
||||
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
|
||||
@ -68,15 +69,12 @@ module icache
|
||||
localparam WORDSPERLINE = BLOCKLEN/`XLEN;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
|
||||
localparam FetchCountThreshold = WORDSPERLINE - 1;
|
||||
|
||||
localparam integer PA_WIDTH = `PA_BITS - 2;
|
||||
localparam integer NUMWAYS = `ICACHE_NUMWAYS;
|
||||
|
||||
|
||||
// Input signals to cache memory
|
||||
logic ICacheMemWriteEnable;
|
||||
logic [BLOCKLEN-1:0] ICacheMemWriteData;
|
||||
logic [`PA_BITS-1:0] FinalPCPF;
|
||||
// Output signals from cache memory
|
||||
logic [31:0] ICacheMemReadData;
|
||||
@ -87,18 +85,11 @@ module icache
|
||||
logic [15:0] SpillDataBlock0;
|
||||
logic spill;
|
||||
logic spillSave;
|
||||
|
||||
logic FetchCountFlag;
|
||||
logic CntEn;
|
||||
|
||||
logic [1:1] SelAdr_q;
|
||||
|
||||
|
||||
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
||||
|
||||
|
||||
logic [`PA_BITS-1:0] PCPSpillF;
|
||||
|
||||
logic CntReset;
|
||||
logic [1:0] SelAdr;
|
||||
logic [INDEXLEN-1:0] RAdr;
|
||||
logic [NUMWAYS-1:0] VictimWay;
|
||||
@ -196,32 +187,6 @@ module icache
|
||||
assign spill = &PCF[$clog2(BLOCKLEN/32)+1:1];
|
||||
|
||||
|
||||
// to compute the fetch address we need to add the bit shifted
|
||||
// counter output to the address.
|
||||
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
||||
|
||||
flopenr #(LOGWPL)
|
||||
FetchCountReg(.clk(clk),
|
||||
.reset(reset | CntReset),
|
||||
.en(CntEn),
|
||||
.d(NextFetchCount),
|
||||
.q(FetchCount));
|
||||
|
||||
assign NextFetchCount = FetchCount + 1'b1;
|
||||
|
||||
|
||||
// store read data from memory interface before writing into SRAM.
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
|
||||
flopenr #(`XLEN) sb(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(ICacheBusAck & (i == FetchCount)),
|
||||
.d(IfuBusHRDATA),
|
||||
.q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
|
||||
// *** read enable may not be necessary.
|
||||
@ -233,17 +198,22 @@ module icache
|
||||
|
||||
assign FinalPCPF = SelAdr_q[1] ? PCPSpillF : PCPF;
|
||||
|
||||
|
||||
// *** CHANGE ME
|
||||
// if not cacheable the offset bits needs to be sent to the EBU.
|
||||
// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
|
||||
assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
|
||||
assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
|
||||
//assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
|
||||
//assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
|
||||
|
||||
//assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
|
||||
assign ICacheBusAdr = {FinalPCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
|
||||
|
||||
assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
|
||||
|
||||
// truncate the offset from PCPF for memory address generation
|
||||
|
||||
assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
|
||||
|
||||
|
||||
icachefsm controller(.clk,
|
||||
.reset,
|
||||
.CPUBusy,
|
||||
@ -252,16 +222,13 @@ module icache
|
||||
.ICacheStallF,
|
||||
.ITLBMissF,
|
||||
.ITLBWriteF,
|
||||
.ExceptionM,
|
||||
.PendingInterruptM,
|
||||
.IgnoreRequest,
|
||||
.ICacheBusAck,
|
||||
.IfuBusFetch,
|
||||
.ICacheFetchLine,
|
||||
.CacheableF,
|
||||
.hit,
|
||||
.FetchCountFlag,
|
||||
.spill,
|
||||
.spillSave,
|
||||
.CntEn,
|
||||
.CntReset,
|
||||
.SelAdr,
|
||||
.LRUWriteEn);
|
||||
|
||||
|
||||
48
wally-pipelined/src/cache/icachefsm.sv
vendored
48
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -35,14 +35,14 @@ module icachefsm
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
input logic IgnoreRequest,
|
||||
input logic CacheableF,
|
||||
|
||||
// BUS interface
|
||||
input logic ICacheBusAck,
|
||||
|
||||
// icache internal inputs
|
||||
input logic hit,
|
||||
input logic FetchCountFlag,
|
||||
input logic spill,
|
||||
|
||||
// icache internal outputs
|
||||
@ -54,12 +54,10 @@ module icachefsm
|
||||
output logic ICacheStallF,
|
||||
|
||||
// Bus interface outputs
|
||||
output logic IfuBusFetch,
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
// icache internal outputs
|
||||
output logic spillSave,
|
||||
output logic CntEn,
|
||||
output logic CntReset,
|
||||
output logic [1:0] SelAdr,
|
||||
output logic LRUWriteEn
|
||||
);
|
||||
@ -119,8 +117,6 @@ module icachefsm
|
||||
|
||||
// Next state logic
|
||||
always_comb begin
|
||||
CntReset = 1'b0;
|
||||
PreCntEn = 1'b0;
|
||||
//IfuBusFetch = 1'b0;
|
||||
ICacheMemWriteEnable = 1'b0;
|
||||
spillSave = 1'b0;
|
||||
@ -132,17 +128,12 @@ module icachefsm
|
||||
STATE_READY: begin
|
||||
SelAdr = 2'b00;
|
||||
ICacheReadEn = 1'b1;
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
|
||||
NextState = STATE_TLB_MISS;
|
||||
end else
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if(ITLBMissF) begin
|
||||
NextState = STATE_READY;
|
||||
SelAdr = 2'b01;
|
||||
ICacheStallF = 1'b0;
|
||||
end
|
||||
else if (hit & ~spill) begin
|
||||
else if (CacheableF & hit & ~spill) begin
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
@ -151,17 +142,15 @@ module icachefsm
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end else if (hit & spill) begin
|
||||
end else if (CacheableF & hit & spill) begin
|
||||
spillSave = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_HIT_SPILL;
|
||||
end else if (~hit & ~spill) begin
|
||||
CntReset = 1'b1;
|
||||
end else if (CacheableF & ~hit & ~spill) begin
|
||||
SelAdr = 2'b01; /// *********(
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else if (~hit & spill) begin
|
||||
CntReset = 1'b1;
|
||||
end else if (CacheableF & ~hit & spill) begin
|
||||
SelAdr = 2'b01;
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
end else begin
|
||||
@ -180,15 +169,13 @@ module icachefsm
|
||||
if (hit) begin
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end else begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_HIT_SPILL_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b10;
|
||||
//IfuBusFetch = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
@ -222,8 +209,7 @@ module icachefsm
|
||||
STATE_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b01;
|
||||
//IfuBusFetch = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
@ -255,9 +241,8 @@ module icachefsm
|
||||
// branch 4 miss spill hit, and 5 miss spill miss
|
||||
STATE_MISS_SPILL_FETCH_WDV: begin
|
||||
SelAdr = 2'b01;
|
||||
PreCntEn = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_MISS_SPILL_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
@ -282,7 +267,6 @@ module icachefsm
|
||||
end
|
||||
STATE_MISS_SPILL_2_START: begin
|
||||
if (~hit) begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||
end else begin
|
||||
ICacheReadEn = 1'b1;
|
||||
@ -299,9 +283,8 @@ module icachefsm
|
||||
end
|
||||
STATE_MISS_SPILL_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b10;
|
||||
PreCntEn = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||
@ -358,10 +341,9 @@ module icachefsm
|
||||
endcase
|
||||
end
|
||||
|
||||
assign CntEn = PreCntEn & ICacheBusAck;
|
||||
assign IfuBusFetch = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
|
||||
assign ICacheFetchLine = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -40,10 +40,10 @@ module ahblite (
|
||||
input logic UnsignedLoadM,
|
||||
input logic [1:0] AtomicMaskedM,
|
||||
// Signals from Instruction Cache
|
||||
input logic [`PA_BITS-1:0] ICacheBusAdr, // *** rename these to match block diagram
|
||||
input logic IfuBusFetch,
|
||||
input logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
input logic IfuBusRead,
|
||||
output logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
output logic ICacheBusAck,
|
||||
output logic IfuBusAck,
|
||||
// Signals from Data Cache
|
||||
input logic [`PA_BITS-1:0] LsuBusAdr,
|
||||
input logic LsuBusRead,
|
||||
@ -100,23 +100,23 @@ module ahblite (
|
||||
case (BusState)
|
||||
IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
|
||||
else if (LsuBusWrite)NextBusState = MEMWRITE;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
MEMREAD: if (~HREADY) NextBusState = MEMREAD;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE; // if (IfuBusFetch still high)
|
||||
else NextBusState = IDLE; // if (IfuBusRead still high)
|
||||
default: NextBusState = IDLE;
|
||||
endcase
|
||||
|
||||
|
||||
// bus outputs
|
||||
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
|
||||
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : ICacheBusAdr[31:0];
|
||||
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : IfuBusAdr[31:0];
|
||||
assign #1 HADDR = AccessAddress;
|
||||
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
||||
assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
|
||||
@ -138,7 +138,7 @@ module ahblite (
|
||||
|
||||
assign IfuBusHRDATA = HRDATA;
|
||||
assign LsuBusHRDATA = HRDATA;
|
||||
assign ICacheBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
||||
assign IfuBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
||||
assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -29,7 +29,7 @@ module hazard(
|
||||
// Detect hazards
|
||||
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
|
||||
(* mark_debug = "true" *) input logic LSUStall, ICacheStallF,
|
||||
(* mark_debug = "true" *) input logic LSUStall, IfuStallF,
|
||||
(* mark_debug = "true" *) input logic FPUStallD, FStallD,
|
||||
(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
|
||||
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
|
||||
@ -59,7 +59,7 @@ module hazard(
|
||||
assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||
assign StallECause = DivBusyE | FDivBusyE;
|
||||
assign StallMCause = 0;
|
||||
assign StallWCause = LSUStall | ICacheStallF;
|
||||
assign StallWCause = LSUStall | IfuStallF;
|
||||
|
||||
assign StallF = StallFCause | StallD;
|
||||
assign StallD = StallDCause | StallE;
|
||||
|
||||
@ -32,11 +32,11 @@ module ifu (
|
||||
input logic FlushF, FlushD, FlushE, FlushM, FlushW,
|
||||
// Fetch
|
||||
input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
input logic ICacheBusAck,
|
||||
input logic IfuBusAck,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
|
||||
output logic [`PA_BITS-1:0] ICacheBusAdr,
|
||||
output logic IfuBusFetch,
|
||||
output logic ICacheStallF,
|
||||
output logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
output logic IfuBusRead,
|
||||
output logic IfuStallF,
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE,
|
||||
input logic PCSrcE,
|
||||
@ -156,6 +156,12 @@ module ifu (
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
|
||||
logic [4:0] InstrClassD, InstrClassE;
|
||||
|
||||
logic ICacheFetchLine;
|
||||
logic BusStall;
|
||||
logic ICacheStallF;
|
||||
logic IgnoreRequest;
|
||||
|
||||
|
||||
|
||||
// *** put memory interface on here, InstrF becomes output
|
||||
@ -167,13 +173,66 @@ module ifu (
|
||||
// 1. ram // controlled by `MEM_IROM
|
||||
// 2. cache // `MEM_ICACHE
|
||||
// 3. wire pass-through
|
||||
icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .IfuBusHRDATA, .ICacheBusAck,
|
||||
.ICacheBusAdr, .IfuBusFetch, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
|
||||
|
||||
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS/`XLEN : `XLEN/8;
|
||||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam integer BLOCKLEN = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS : `XLEN;
|
||||
localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
|
||||
|
||||
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
|
||||
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
|
||||
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
logic [BLOCKLEN-1:0] ICacheMemWriteData;
|
||||
logic ICacheBusAck;
|
||||
logic [`PA_BITS-1:0] LocalIfuBusAdr;
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic SelUncachedAdr;
|
||||
|
||||
|
||||
// *** bug: on spill the second memory request does not go through the mmu(skips tlb, pmp, and pma checkers)
|
||||
// also it is possible to have any above fault on the spilled accesses.
|
||||
// I think the solution is to move the spill logic into the ifu using the busfsm and ensuring
|
||||
// the mmu sees the spilled address.
|
||||
|
||||
icache icache(.clk, .reset, .CPUBusy(StallF), .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
|
||||
.ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
|
||||
.ICacheFetchLine,
|
||||
.CacheableF,
|
||||
.PCNextF(PCNextFPhys),
|
||||
.PCPF(PCPFmmu),
|
||||
.PCF,
|
||||
.InvalidateICacheM);
|
||||
.PCNextF(PCNextFPhys),
|
||||
.PCPF(PCPFmmu),
|
||||
.PCF,
|
||||
.InvalidateICacheM);
|
||||
|
||||
|
||||
genvar index;
|
||||
generate
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk(clk),
|
||||
.en(IfuBusAck & IfuBusRead & (index == WordCount)),
|
||||
.d(IfuBusHRDATA),
|
||||
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign LocalIfuBusAdr = SelUncachedAdr ? PCPFmmu : ICacheBusAdr;
|
||||
assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL)
|
||||
busfm(.clk, .reset, .IgnoreRequest,
|
||||
.LsuRWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0),
|
||||
.LsuBusAck(IfuBusAck),
|
||||
.CPUBusy(StallF), .CacheableM(CacheableF),
|
||||
.BusStall, .LsuBusWrite(), .LsuBusRead(IfuBusRead), .DCacheBusAck(ICacheBusAck),
|
||||
.BusCommittedM(), .SelUncachedAdr(SelUncachedAdr), .WordCount);
|
||||
|
||||
assign IfuStallF = ICacheStallF | BusStall;
|
||||
|
||||
assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
|
||||
|
||||
@ -232,23 +291,12 @@ module ifu (
|
||||
// I am making the port connection explicit for now as I want to see them and they will be changing.
|
||||
|
||||
bpred bpred(.clk, .reset,
|
||||
.StallF, .StallD, .StallE,
|
||||
.FlushF, .FlushD, .FlushE,
|
||||
|
||||
.PCNextF(PCNextF),
|
||||
.BPPredPCF(BPPredPCF),
|
||||
.SelBPPredF(SelBPPredF),
|
||||
.PCE(PCE),
|
||||
.PCSrcE(PCSrcE),
|
||||
.IEUAdrE(IEUAdrE),
|
||||
.PCD(PCD),
|
||||
.PCLinkE(PCLinkE),
|
||||
.InstrClassE(InstrClassE),
|
||||
.BPPredWrongE(BPPredWrongE),
|
||||
.BPPredDirWrongE(BPPredDirWrongE),
|
||||
.BTBPredPCWrongE(BTBPredPCWrongE),
|
||||
.RASPredPCWrongE(RASPredPCWrongE),
|
||||
.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
|
||||
.StallF, .StallD, .StallE,
|
||||
.FlushF, .FlushD, .FlushE,
|
||||
.PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
|
||||
.PCD, .PCLinkE, .InstrClassE, .BPPredWrongE, .BPPredDirWrongE,
|
||||
.BTBPredPCWrongE, .RASPredPCWrongE, .BPPredClassNonCFIWrongE);
|
||||
|
||||
end else begin : bpred
|
||||
assign BPPredPCF = {`XLEN{1'b0}};
|
||||
assign SelBPPredF = 1'b0;
|
||||
@ -291,13 +339,11 @@ module ifu (
|
||||
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
|
||||
|
||||
// Misaligned PC logic
|
||||
|
||||
generate
|
||||
if (`C_SUPPORTED) // C supports compressed instructions on halfword boundaries
|
||||
assign misaligned = PCNextF[0];
|
||||
else // instructions must be on word boundaries
|
||||
assign misaligned = |PCNextF[1:0];
|
||||
endgenerate
|
||||
// instruction address misalignment is generated by the target of control flow instructions, not
|
||||
// the fetch itself.
|
||||
assign misaligned = PCNextF[0] | (PCNextF[1] & ~`C_SUPPORTED);
|
||||
// do we really need to have check if the instruction is control flow? Yes
|
||||
// Branches are updated in the execution stage but traps are updated in the memory stage.
|
||||
|
||||
// pipeline misaligned faults to M stage
|
||||
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
|
||||
|
||||
@ -125,7 +125,7 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
|
||||
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
|
||||
|
||||
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
|
||||
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
|
||||
|
||||
@ -113,7 +113,7 @@ module wallypipelinedhart (
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic ICacheStallF;
|
||||
logic IfuStallF;
|
||||
logic LSUStall;
|
||||
|
||||
|
||||
@ -128,10 +128,10 @@ module wallypipelinedhart (
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic [`PA_BITS-1:0] IfuBusAdr;
|
||||
logic [`XLEN-1:0] IfuBusHRDATA;
|
||||
logic IfuBusFetch;
|
||||
logic ICacheBusAck;
|
||||
logic IfuBusRead;
|
||||
logic IfuBusAck;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [`PA_BITS-1:0] LsuBusAdr;
|
||||
@ -164,8 +164,8 @@ module wallypipelinedhart (
|
||||
|
||||
.ExceptionM, .PendingInterruptM,
|
||||
// Fetch
|
||||
.IfuBusHRDATA, .ICacheBusAck, .PCF, .ICacheBusAdr,
|
||||
.IfuBusFetch, .ICacheStallF,
|
||||
.IfuBusHRDATA, .IfuBusAck, .PCF, .IfuBusAdr,
|
||||
.IfuBusRead, .IfuStallF,
|
||||
|
||||
// Execute
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
|
||||
@ -277,8 +277,8 @@ module wallypipelinedhart (
|
||||
ahblite ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
|
||||
.ICacheBusAdr, // *** rename these to match block diagram
|
||||
.IfuBusFetch, .IfuBusHRDATA, .ICacheBusAck,
|
||||
.IfuBusAdr,
|
||||
.IfuBusRead, .IfuBusHRDATA, .IfuBusAck,
|
||||
// Signals from Data Cache
|
||||
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
|
||||
.LsuBusHRDATA,
|
||||
@ -294,7 +294,7 @@ module wallypipelinedhart (
|
||||
hazard hzu(
|
||||
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
|
||||
.LSUStall, .ICacheStallF,
|
||||
.LSUStall, .IfuStallF,
|
||||
.FPUStallD, .FStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user