forked from Github_Repos/cvw
Changed names of Icache signals.
This commit is contained in:
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a37c7515bd
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9bcb105aa4
@ -175,11 +175,11 @@ add wave -noupdate -group icache -expand -group {fsm out and control} /testbench
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/IfuBusFetch
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
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@ -187,7 +187,7 @@ add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
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add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/IfuBusFetch
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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39
wally-pipelined/src/cache/icache.sv
vendored
39
wally-pipelined/src/cache/icache.sv
vendored
@ -37,11 +37,11 @@ module icache
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input logic ExceptionM, PendingInterruptM,
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// Data read in from the ebu unit
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(* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF,
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(* mark_debug = "true" *) input logic InstrAckF,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA,
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(* mark_debug = "true" *) input logic ICacheBusAck,
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// Read requested from the ebu unit
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF,
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(* mark_debug = "true" *) output logic InstrReadF,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
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(* mark_debug = "true" *) output logic IfuBusFetch,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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// High if the icache is requesting a stall
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@ -77,7 +77,7 @@ module icache
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// Input signals to cache memory
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logic ICacheMemWriteEnable;
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logic [BLOCKLEN-1:0] ICacheMemWriteData;
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logic [`PA_BITS-1:0] PCTagF;
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logic [`PA_BITS-1:0] FinalPCPF;
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// Output signals from cache memory
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logic [31:0] ICacheMemReadData;
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logic ICacheReadEn;
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@ -111,7 +111,7 @@ module icache
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logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0];
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logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF;
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logic [`PA_BITS-1:0] BasePAdrMaskedF;
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logic [OFFSETLEN-1:0] BasePAdrOffsetF;
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@ -121,7 +121,7 @@ module icache
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// on spill we want to get the first 2 bytes of the next cache block.
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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// simply add 2 to land on the next cache block.
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assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
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assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10};
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mux3 #(INDEXLEN)
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AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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@ -134,7 +134,7 @@ module icache
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cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
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.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
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MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
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.PAdr(PCTagF),
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.PAdr(FinalPCPF),
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.WriteEnable(SRAMWayWriteEnable),
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.VDWriteEnable(1'b0),
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.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
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@ -154,7 +154,7 @@ module icache
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cachereplacementpolicy(.clk, .reset,
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.WayHit,
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.VictimWay,
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.LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.LsuPAdrM(FinalPCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.RAdr,
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.LRUWriteEn);
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end else begin
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@ -177,7 +177,7 @@ module icache
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assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
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endgenerate
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assign ICacheMemReadData = ReadLineSetsF[PCTagF[$clog2(BLOCKLEN / 32) + 1 : 1]];
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assign ICacheMemReadData = ReadLineSetsF[FinalPCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
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// spills require storing the first cache block so it can merged
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// with the second
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@ -216,8 +216,8 @@ module icache
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for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
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flopenr #(`XLEN) sb(.clk(clk),
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.reset(reset),
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.en(InstrAckF & (i == FetchCount)),
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.d(InstrInF),
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.en(ICacheBusAck & (i == FetchCount)),
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.d(IfuBusHRDATA),
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.q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]));
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end
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endgenerate
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@ -231,17 +231,14 @@ module icache
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.d(SelAdr[1]),
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.q(SelAdr_q[1]));
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assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF;
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// unlike the dcache the victim is never dirty so no eviction is necessary.
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assign BasePAdrF = PCTagF;
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assign FinalPCPF = SelAdr_q[1] ? PCPSpillF : PCPF;
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// if not cacheable the offset bits needs to be sent to the EBU.
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// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
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assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : BasePAdrF[OFFSETLEN-1:0];
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assign BasePAdrMaskedF = {BasePAdrF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
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assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
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assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
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assign InstrPAdrF = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
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assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
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// truncate the offset from PCPF for memory address generation
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@ -257,8 +254,8 @@ module icache
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.ITLBWriteF,
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.ExceptionM,
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.PendingInterruptM,
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.InstrAckF,
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.InstrReadF,
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.ICacheBusAck,
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.IfuBusFetch,
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.hit,
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.FetchCountFlag,
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.spill,
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26
wally-pipelined/src/cache/icachefsm.sv
vendored
26
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -38,7 +38,7 @@ module icachefsm
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input logic ExceptionM, PendingInterruptM,
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// BUS interface
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input logic InstrAckF,
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input logic ICacheBusAck,
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// icache internal inputs
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input logic hit,
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@ -54,7 +54,7 @@ module icachefsm
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output logic ICacheStallF,
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// Bus interface outputs
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output logic InstrReadF,
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output logic IfuBusFetch,
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// icache internal outputs
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output logic spillSave,
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@ -121,7 +121,7 @@ module icachefsm
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always_comb begin
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CntReset = 1'b0;
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PreCntEn = 1'b0;
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//InstrReadF = 1'b0;
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//IfuBusFetch = 1'b0;
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ICacheMemWriteEnable = 1'b0;
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spillSave = 1'b0;
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SelAdr = 2'b00;
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@ -186,9 +186,9 @@ module icachefsm
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end
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STATE_HIT_SPILL_MISS_FETCH_WDV: begin
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SelAdr = 2'b10;
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//InstrReadF = 1'b1;
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//IfuBusFetch = 1'b1;
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PreCntEn = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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if (FetchCountFlag & ICacheBusAck) begin
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NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
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@ -221,9 +221,9 @@ module icachefsm
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// branch 3 miss no spill
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STATE_MISS_FETCH_WDV: begin
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SelAdr = 2'b01;
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//InstrReadF = 1'b1;
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//IfuBusFetch = 1'b1;
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PreCntEn = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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if (FetchCountFlag & ICacheBusAck) begin
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NextState = STATE_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_FETCH_WDV;
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@ -256,8 +256,8 @@ module icachefsm
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STATE_MISS_SPILL_FETCH_WDV: begin
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SelAdr = 2'b01;
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PreCntEn = 1'b1;
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//InstrReadF = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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//IfuBusFetch = 1'b1;
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if (FetchCountFlag & ICacheBusAck) begin
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NextState = STATE_MISS_SPILL_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_SPILL_FETCH_WDV;
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@ -300,8 +300,8 @@ module icachefsm
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STATE_MISS_SPILL_MISS_FETCH_WDV: begin
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SelAdr = 2'b10;
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PreCntEn = 1'b1;
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//InstrReadF = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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//IfuBusFetch = 1'b1;
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if (FetchCountFlag & ICacheBusAck) begin
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NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
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@ -358,8 +358,8 @@ module icachefsm
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endcase
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end
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assign CntEn = PreCntEn & InstrAckF;
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assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
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assign CntEn = PreCntEn & ICacheBusAck;
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assign IfuBusFetch = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
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(CurrState == STATE_MISS_FETCH_WDV) ||
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(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
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(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
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@ -40,10 +40,10 @@ module ahblite (
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input logic UnsignedLoadM,
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input logic [1:0] AtomicMaskedM,
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// Signals from Instruction Cache
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input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic InstrReadF,
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output logic [`XLEN-1:0] InstrRData,
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output logic InstrAckF,
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input logic [`PA_BITS-1:0] ICacheBusAdr, // *** rename these to match block diagram
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input logic IfuBusFetch,
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output logic [`XLEN-1:0] IfuBusHRDATA,
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output logic ICacheBusAck,
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// Signals from Data Cache
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input logic [`PA_BITS-1:0] LsuBusAdr,
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input logic LsuBusRead,
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@ -100,23 +100,23 @@ module ahblite (
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case (BusState)
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IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (LsuBusWrite)NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else if (IfuBusFetch) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else if (IfuBusFetch) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else if (IfuBusFetch) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (InstrReadF still high)
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else NextBusState = IDLE; // if (IfuBusFetch still high)
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default: NextBusState = IDLE;
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endcase
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
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assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0];
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assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : ICacheBusAdr[31:0];
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assign #1 HADDR = AccessAddress;
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
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@ -136,9 +136,9 @@ module ahblite (
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// *** assumes AHBW = XLEN
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assign InstrRData = HRDATA;
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assign IfuBusHRDATA = HRDATA;
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assign LsuBusHRDATA = HRDATA;
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assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
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assign ICacheBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
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assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
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endmodule
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@ -31,11 +31,11 @@ module ifu (
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Fetch
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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input logic [`XLEN-1:0] IfuBusHRDATA,
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input logic ICacheBusAck,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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output logic [`PA_BITS-1:0] InstrPAdrF,
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output logic InstrReadF,
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output logic [`PA_BITS-1:0] ICacheBusAdr,
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output logic IfuBusFetch,
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output logic ICacheStallF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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@ -159,16 +159,16 @@ module ifu (
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// *** put memory interface on here, InstrF becomes output
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//assign InstrPAdrF = PCF; // *** no MMU
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//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
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// assign InstrReadF = 1; // *** & ICacheMissF; add later
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//assign ICacheBusAdr = PCF; // *** no MMU
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//assign IfuBusFetch = ~StallD; // *** & ICacheMissF; add later
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// assign IfuBusFetch = 1; // *** & ICacheMissF; add later
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// conditional
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// 1. ram // controlled by `MEM_IROM
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// 2. cache // `MEM_ICACHE
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// 3. wire pass-through
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icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
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.InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
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icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .IfuBusHRDATA, .ICacheBusAck,
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.ICacheBusAdr, .IfuBusFetch, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
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.CacheableF,
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.PCNextF(PCNextFPhys),
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.PCPF(PCPFmmu),
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@ -128,10 +128,10 @@ module wallypipelinedhart (
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logic CommittedM;
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// AHB ifu interface
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logic [`PA_BITS-1:0] InstrPAdrF;
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logic [`XLEN-1:0] InstrRData;
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logic InstrReadF;
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logic InstrAckF;
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logic [`PA_BITS-1:0] ICacheBusAdr;
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logic [`XLEN-1:0] IfuBusHRDATA;
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logic IfuBusFetch;
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logic ICacheBusAck;
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// AHB LSU interface
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logic [`PA_BITS-1:0] LsuBusAdr;
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@ -164,8 +164,8 @@ module wallypipelinedhart (
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.ExceptionM, .PendingInterruptM,
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// Fetch
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.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF,
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.InstrReadF, .ICacheStallF,
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.IfuBusHRDATA, .ICacheBusAck, .PCF, .ICacheBusAdr,
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.IfuBusFetch, .ICacheStallF,
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// Execute
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.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
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@ -277,8 +277,8 @@ module wallypipelinedhart (
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ahblite ebu(// IFU connections
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.clk, .reset,
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.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
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.InstrPAdrF, // *** rename these to match block diagram
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.InstrReadF, .InstrRData, .InstrAckF,
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.ICacheBusAdr, // *** rename these to match block diagram
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.IfuBusFetch, .IfuBusHRDATA, .ICacheBusAck,
|
||||
// Signals from Data Cache
|
||||
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
|
||||
.LsuBusHRDATA,
|
||||
|
Loading…
Reference in New Issue
Block a user