forked from Github_Repos/cvw
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
This commit is contained in:
Ross Thompson
parent
86514a6a23
commit
b6c9d01f8b
@ -434,33 +434,36 @@ add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine
|
||||
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfm/BusCurrState
|
||||
add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfm/LsuBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheFetchLine
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {0 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
@ -476,4 +479,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {752 ns}
|
||||
WaveRestoreZoom {1238897 ns} {1239273 ns}
|
||||
|
||||
1
wally-pipelined/src/cache/icache.sv
vendored
1
wally-pipelined/src/cache/icache.sv
vendored
@ -225,6 +225,7 @@ module icache
|
||||
.IgnoreRequest,
|
||||
.ICacheBusAck,
|
||||
.ICacheFetchLine,
|
||||
.CacheableF,
|
||||
.hit,
|
||||
.spill,
|
||||
.spillSave,
|
||||
|
||||
9
wally-pipelined/src/cache/icachefsm.sv
vendored
9
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -36,6 +36,7 @@ module icachefsm
|
||||
input logic ITLBWriteF,
|
||||
|
||||
input logic IgnoreRequest,
|
||||
input logic CacheableF,
|
||||
|
||||
// BUS interface
|
||||
input logic ICacheBusAck,
|
||||
@ -132,7 +133,7 @@ module icachefsm
|
||||
SelAdr = 2'b01;
|
||||
ICacheStallF = 1'b0;
|
||||
end
|
||||
else if (hit & ~spill) begin
|
||||
else if (CacheableF & hit & ~spill) begin
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
@ -141,15 +142,15 @@ module icachefsm
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end else if (hit & spill) begin
|
||||
end else if (CacheableF & hit & spill) begin
|
||||
spillSave = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_HIT_SPILL;
|
||||
end else if (~hit & ~spill) begin
|
||||
end else if (CacheableF & ~hit & ~spill) begin
|
||||
SelAdr = 2'b01; /// *********(
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else if (~hit & spill) begin
|
||||
end else if (CacheableF & ~hit & spill) begin
|
||||
SelAdr = 2'b01;
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
end else begin
|
||||
|
||||
@ -189,7 +189,11 @@ module ifu (
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic SelUncachedAdr;
|
||||
|
||||
|
||||
|
||||
// *** bug: on spill the second memory request does not go through the mmu(skips tlb, pmp, and pma checkers)
|
||||
// also it is possible to have any above fault on the spilled accesses.
|
||||
// I think the solution is to move the spill logic into the ifu using the busfsm and ensuring
|
||||
// the mmu sees the spilled address.
|
||||
|
||||
icache icache(.clk, .reset, .CPUBusy(StallF), .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
|
||||
.ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
|
||||
|
||||
@ -125,7 +125,7 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
|
||||
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
|
||||
|
||||
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
|
||||
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user