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Replaced && and || with & and | in non-fp files per new style guidelines

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This commit is contained in:
David Harris 2022-01-02 21:47:21 +00:00
parent 9693110857
commit d909e8f371
35 changed files with 262 additions and 262 deletions
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6
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -341,9 +341,9 @@ module icachefsm
endcase
end
assign ICacheFetchLine = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
(CurrState == STATE_MISS_FETCH_WDV) ||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
assign ICacheFetchLine = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_SPILL_FETCH_WDV) |
(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
endmodule

6
wally-pipelined/src/ebu/ahblite.sv
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@ -115,7 +115,7 @@ module ahblite (
// bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : IfuBusAdr[31:0];
assign #1 HADDR = AccessAddress;
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
@ -138,7 +138,7 @@ module ahblite (
assign IfuBusHRDATA = HRDATA;
assign LsuBusHRDATA = HRDATA;
assign IfuBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
assign IfuBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD);
assign LsuBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE);
endmodule

6
wally-pipelined/src/fpu/fsm_fpdiv.sv
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@ -75,7 +75,7 @@ module fsm_fpdiv (
sel_muxr = 1'b0;
next_state = S0;
end
else if (start==1'b1 && op_type==1'b0)
else if (start==1'b1 & op_type==1'b0)
begin
done = 1'b0;
divBusy = 1'b1;
@ -89,8 +89,8 @@ module fsm_fpdiv (
sel_muxb = 3'b001;
sel_muxr = 1'b0;
next_state = S1;
end // if (start==1'b1 && op_type==1'b0)
else if (start==1'b1 && op_type==1'b1)
end // if (start==1'b1 & op_type==1'b0)
else if (start==1'b1 & op_type==1'b1)
begin
done = 1'b0;
divBusy = 1'b1;

10
wally-pipelined/src/hazard/hazard.sv
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@ -55,7 +55,7 @@ module hazard(
// A stage must stall if the next stage is stalled
// If any stages are stalled, the first stage that isn't stalled must flush.
assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE);
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE | FDivBusyE;
assign StallMCause = 0;
@ -67,10 +67,10 @@ module hazard(
assign StallM = StallMCause | StallW;
assign StallW = StallWCause;
assign FirstUnstalledD = (~StallD && StallF);
assign FirstUnstalledE = (~StallE && StallD);
assign FirstUnstalledM = (~StallM && StallE);
assign FirstUnstalledW = (~StallW && StallM);
assign FirstUnstalledD = ~StallD & StallF;
assign FirstUnstalledE = ~StallE & StallD;
assign FirstUnstalledM = ~StallM & StallE;
assign FirstUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign FlushF = BPPredWrongE | InvalidateICacheM;

10
wally-pipelined/src/ieu/controller.sv
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@ -134,16 +134,16 @@ module controller(
ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0;; // amo
end else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000)
7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
else if (Funct7D == 7'b0000001 && `M_SUPPORTED)
else if (Funct7D == 7'b0000001 & `M_SUPPORTED)
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/Divide
else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64)
7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64)
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64)
else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64)
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
@ -168,7 +168,7 @@ module controller(
// *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD && InstrD[13]); // Don't write if setting or clearing zeros
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
assign sltD = (Funct3D == 3'b010);

2
wally-pipelined/src/ifu/decompress.sv
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@ -124,7 +124,7 @@ module decompress (
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
else // if (instr16[6:5] == 2'b11)
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
else if (instr16[12:10] == 3'b111 && `XLEN > 32)
else if (instr16[12:10] == 3'b111 & `XLEN > 32)
if (instr16[6:5] == 2'b00)
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
else if (instr16[6:5] == 2'b01)

8
wally-pipelined/src/ifu/ifu.sv
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@ -348,10 +348,10 @@ module ifu (
// the branch predictor needs a compact decoding of the instruction class.
// *** consider adding in the alternate return address x5 for returns.
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01 && (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
assign InstrClassD[1] = InstrD[6:0] == 7'h6F && (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
// Misaligned PC logic

2
wally-pipelined/src/ifu/localHistoryPredictor.sv
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@ -71,7 +71,7 @@ module localHistoryPredictor
flopenr #(k) LocalHistoryRegister(.clk(clk),
.reset(reset),
.en(UpdateEN && (index == UpdatePCIndex)),
.en(UpdateEN & (index == UpdatePCIndex)),
.d(LHRFNext),
.q(LHRNextF[index]));
end

10
wally-pipelined/src/lsu/lrsc.sv
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@ -43,14 +43,14 @@ module lrsc
logic lrM, scM, WriteAdrMatchM;
logic SquashSCM;
assign lrM = MemReadM && LsuAtomicM[0];
assign scM = PreLsuRWM[0] && LsuAtomicM[0];
assign WriteAdrMatchM = PreLsuRWM[0] && (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign SquashSCM = scM && ~WriteAdrMatchM;
assign lrM = MemReadM & LsuAtomicM[0];
assign scM = PreLsuRWM[0] & LsuAtomicM[0];
assign WriteAdrMatchM = PreLsuRWM[0] & (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
assign SquashSCM = scM & ~WriteAdrMatchM;
assign LsuRWM = SquashSCM ? 2'b00 : PreLsuRWM;
always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
else if (scM | WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
else ReservationValidM = ReservationValidW; // otherwise don't change valid
end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LsuPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid

2
wally-pipelined/src/mmu/adrdec.sv
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@ -46,7 +46,7 @@ module adrdec (
// determine if legal size of access is being made (byte, halfword, word, doubleword)
assign SizeValid = SizeMask[Size];
assign Sel = Match && Supported && AccessValid && SizeValid;
assign Sel = Match & Supported & AccessValid & SizeValid;
endmodule

14
wally-pipelined/src/mmu/hptw.sv
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@ -89,7 +89,7 @@ module hptw
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
assign {Executable, Writable, Readable, Valid} = PTE[3:0];
assign LeafPTE = Executable | Writable | Readable;
assign ValidPTE = Valid && ~(Writable && ~Readable);
assign ValidPTE = Valid & ~(Writable & ~Readable);
assign ValidLeafPTE = ValidPTE & LeafPTE;
assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
@ -162,28 +162,28 @@ module hptw
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
else NextWalkerState = L2_ADR;
// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
// LEVEL3: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
// else NextWalkerState = FAULT;
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
else NextWalkerState = LEAF;
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
else NextWalkerState = L1_ADR;
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
// LEVEL2: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
// else NextWalkerState = FAULT;
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
else NextWalkerState = LEAF;
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
else NextWalkerState = L0_ADR;
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
// LEVEL1: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
// else NextWalkerState = FAULT;
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
L0_ADR: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
else NextWalkerState = LEAF;
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;

6
wally-pipelined/src/mmu/pmachecker.sv
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@ -59,8 +59,8 @@ module pmachecker (
// Detect access faults
assign PMAAccessFault = SelRegions[8] & AccessRWX;
assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
assign PMAStoreAccessFaultM = WriteAccessM & PMAAccessFault;
endmodule

4
wally-pipelined/src/mmu/pmpadrdec.sv
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@ -61,7 +61,7 @@ module pmpadrdec (
assign CurrentAdrFull = {PMPAdr[`PA_BITS-3:0], 2'b00};
assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
assign PAgePMPAdrOut = ~PAltPMPAdr;
assign TORMatch = PAgePMPAdrIn && PAltPMPAdr;
assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
// Naturally aligned regions
logic [`PA_BITS-1:0] NAMask, NABase;
@ -75,7 +75,7 @@ module pmpadrdec (
assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range
assign Match = (AdrMode == TOR) ? TORMatch :
(AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
(AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
0;
assign L = PMPCfg[7] & FirstMatch;

6
wally-pipelined/src/mmu/pmpchecker.sv
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@ -70,9 +70,9 @@ module pmpchecker (
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
assign PMPInstrAccessFaultF = EnforcePMP && ExecuteAccessF && ~|X;
assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W;
assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R;
assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|X;
assign PMPStoreAccessFaultM = EnforcePMP & WriteAccessM & ~|W;
assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|R;
end else begin: pmpchecker // no checker
assign PMPInstrAccessFaultF = 0;
assign PMPLoadAccessFaultM = 0;

10
wally-pipelined/src/mmu/tlbcamline.sv
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@ -69,7 +69,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
// Calculate the actual match value based on the input vpn and the page type.
// For example, a megapage in SV32 only cares about VPN[1], so VPN[0]
// should automatically match.
assign Match0 = (Query0 == Key0) || (PageType[0]); // least signifcant section
assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section
assign Match1 = (Query1 == Key1);
assign Match = Match0 & Match1 & MatchASID & Valid;
@ -84,10 +84,10 @@ module tlbcamline #(parameter KEY_BITS = 20,
// Calculate the actual match value based on the input vpn and the page type.
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
// should automatically match.
assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
assign Match3 = (Query3 == Key3) || SV39Mode; // this should always match in sv39 because they aren't used
assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section
assign Match1 = (Query1 == Key1) | (PageType > 2'd1);
assign Match2 = (Query2 == Key2) | (PageType > 2'd2);
assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used
assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
end

16
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -95,28 +95,28 @@ module tlbcontrol #(parameter ITLB = 0) (
// User mode may only execute user mode pages, and supervisor mode may
// only execute non-user mode pages.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
((EffectivePrivilegeMode == `S_MODE) && PTE_U);
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U);
// fault for software handling if access bit is off
assign DAPageFault = ~PTE_A;
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end else begin:dtlb // Data TLB fault checking
logic ImproperPrivilege, InvalidRead, InvalidWrite;
// User mode may only load/store from user mode pages, and supervisor mode
// may only access user mode pages when STATUS_SUM is low.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
((EffectivePrivilegeMode == `S_MODE) && PTE_U && ~STATUS_SUM);
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM);
// Check for read error. Reads are invalid when the page is not readable
// (and executable pages are not readable) or when the page is neither
// readable nor executable (and executable pages are readable).
assign InvalidRead = ReadAccess && ~PTE_R && (~STATUS_MXR | ~PTE_X);
assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
// Check for write error. Writes are invalid when the page's write bit is
// low.
assign InvalidWrite = WriteAccess && ~PTE_W;
assign InvalidWrite = WriteAccess & ~PTE_W;
// Fault for software handling if access bit is off or writing a page with dirty bit off
assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D;
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end
endgenerate

2
wally-pipelined/src/mmu/tlblru.sv
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@ -47,6 +47,6 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
assign RUBitsAccessed = AccessLines | RUBits;
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
// *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
endmodule

14
wally-pipelined/src/privileged/csr.sv
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@ -108,8 +108,8 @@ module csr #(parameter
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
assign CSRUWriteM = CSRWriteM;
csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
@ -161,9 +161,9 @@ module csr #(parameter
flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
// merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
(CSRAdrM[9:8] == 2'b01 && PrivilegeModeW == `U_MODE);
assign IllegalCSRAccessM = ((IllegalCSRCAccessM && IllegalCSRMAccessM &&
IllegalCSRSAccessM && IllegalCSRUAccessM && IllegalCSRNAccessM ||
InsufficientCSRPrivilegeM) && CSRReadM) || IllegalCSRMWriteReadonlyM;
assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) |
(CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM &
IllegalCSRSAccessM & IllegalCSRUAccessM & IllegalCSRNAccessM |
InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
endmodule

20
wally-pipelined/src/privileged/csrc.sv
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@ -100,7 +100,7 @@ module csrc #(parameter
// Counter update and write logic
for (i = 0; i < `COUNTERS; i = i+1) begin
assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);
assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
@ -110,7 +110,7 @@ module csrc #(parameter
logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
assign WriteHPMCOUNTERHM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERHBASE + i);
assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
@ -123,16 +123,16 @@ module csrc #(parameter
// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
always_comb
if (PrivilegeModeW == `M_MODE ||
MCOUNTEREN_REGW[CounterNumM] && (!`S_SUPPORTED || PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
if (PrivilegeModeW == `M_MODE |
MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
IllegalCSRCAccessM = 0;
if (`XLEN==64) begin // 64-bit counter reads
// Veri lator doesn't realize this only occurs for XLEN=64
/* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
/* verilator lint_on WIDTH */
else if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else begin
CSRCReadValM = 0;
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
@ -143,10 +143,10 @@ module csrc #(parameter
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
/* verilator lint_on WIDTH */
else if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= MHPMCOUNTERHBASE && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERHBASE && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else begin
CSRCReadValM = 0;
IllegalCSRCAccessM = 1; // requested CSR doesn't exist

8
wally-pipelined/src/privileged/csri.sv
View File

@ -61,10 +61,10 @@ module csri #(parameter
end
// Interrupt Write Enables
assign WriteMIPM = CSRMWriteM && (CSRAdrM == MIP) && ~StallW;
assign WriteMIEM = CSRMWriteM && (CSRAdrM == MIE) && ~StallW;
assign WriteSIPM = CSRSWriteM && (CSRAdrM == SIP) && ~StallW;
assign WriteSIEM = CSRSWriteM && (CSRAdrM == SIE) && ~StallW;
assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & ~StallW;
assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & ~StallW;
assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & ~StallW;
assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & ~StallW;
// Interrupt Pending and Enable Registers
// MEIP, MTIP, MSIP are read-only

30
wally-pipelined/src/privileged/csrm.sv
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@ -128,18 +128,18 @@ module csrm #(parameter
assign MHARTID_REGW = 0;
// Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS) && ~StallW;
assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC) && ~StallW;
assign WriteMEDELEGM = CSRMWriteM && (CSRAdrM == MEDELEG) && ~StallW;
assign WriteMIDELEGM = CSRMWriteM && (CSRAdrM == MIDELEG) && ~StallW;
assign WriteMSCRATCHM = CSRMWriteM && (CSRAdrM == MSCRATCH) && ~StallW;
assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC)) && ~StallW;
assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE)) && ~StallW;
assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL)) && ~StallW;
assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN) && ~StallW;
assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT) && ~StallW;
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & ~StallW;
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & ~StallW;
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & ~StallW;
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & ~StallW;
assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & ~StallW;
assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & ~StallW;
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & ~StallW;
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & ~StallW;
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & ~StallW;
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & ~StallW;
assign IllegalCSRMWriteReadonlyM = CSRMWriteM && (CSRAdrM == MVENDORID || CSRAdrM == MARCHID || CSRAdrM == MIMPID || CSRAdrM == MHARTID);
assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
// CSRs
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
@ -173,11 +173,11 @@ module csrm #(parameter
logic [5:0] entry;
always_comb begin
entry = '0;
IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &&
(CSRAdrM == MEDELEG || CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
if (CSRAdrM >= PMPADDR0 && CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &
(CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
else if (CSRAdrM >= PMPCFG0 && CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
if (`XLEN==64) begin
entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],

10
wally-pipelined/src/privileged/csrn.sv
View File

@ -58,11 +58,11 @@ module csrn #(parameter
logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
// Write enables
assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS) && ~StallW;
assign WriteUTVECM = CSRNWriteM && (CSRAdrM == UTVEC) && ~StallW;
assign WriteUEPCM = UTrapM | (CSRNWriteM && (CSRAdrM == UEPC)) && ~StallW;
assign WriteUCAUSEM = UTrapM | (CSRNWriteM && (CSRAdrM == UCAUSE)) && ~StallW;
assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)) && ~StallW;
assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & ~StallW;
assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & ~StallW;
assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & ~StallW;
assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & ~StallW;
assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & ~StallW;
// CSRs
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);

24
wally-pipelined/src/privileged/csrs.sv
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@ -77,14 +77,14 @@ module csrs #(parameter
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS) && ~StallW;
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC) && ~StallW;
assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH) && ~StallW;
assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)) && ~StallW;
assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)) && ~StallW;
assign WriteSTVALM = STrapM | (CSRSWriteM && (CSRAdrM == STVAL)) && ~StallW;
assign WriteSATPM = CSRSWriteM && (CSRAdrM == SATP) && (PrivilegeModeW == `M_MODE || ~STATUS_TVM) && ~StallW;
assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW;
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & ~StallW;
assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & ~StallW;
assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & ~StallW;
assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & ~StallW;
assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & ~StallW;
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & ~StallW;
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & ~StallW;
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & ~StallW;
// CSRs
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0
@ -105,8 +105,8 @@ module csrs #(parameter
end
if (`N_SUPPORTED) begin:nregs
logic WriteSEDELEGM, WriteSIDELEGM;
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
assign WriteSEDELEGM = CSRSWriteM & (CSRAdrM == SEDELEG);
assign WriteSIDELEGM = CSRSWriteM & (CSRAdrM == SIDELEG);
flopenr #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, SEDELEG_REGW);
flopenr #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, SIDELEG_REGW);
end else begin
@ -116,7 +116,7 @@ module csrs #(parameter
// CSR Reads
always_comb begin:csrr
IllegalCSRSAccessM = !(`N_SUPPORTED) && (CSRAdrM == SEDELEG || CSRAdrM == SIDELEG); // trap on DELEG register access when no N-mode
IllegalCSRSAccessM = !(`N_SUPPORTED) & (CSRAdrM == SEDELEG | CSRAdrM == SIDELEG); // trap on DELEG register access when no N-mode
case (CSRAdrM)
SSTATUS: CSRSReadValM = SSTATUS_REGW;
STVEC: CSRSReadValM = STVEC_REGW;
@ -130,7 +130,7 @@ module csrs #(parameter
SEPC: CSRSReadValM = SEPC_REGW;
SCAUSE: CSRSReadValM = SCAUSE_REGW;
STVAL: CSRSReadValM = STVAL_REGW;
SATP: if (`MEM_VIRTMEM && (PrivilegeModeW == `M_MODE || ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
SATP: if (`MEM_VIRTMEM & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
else begin
CSRSReadValM = 0;
if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;

8
wally-pipelined/src/privileged/csrsr.sv
View File

@ -96,14 +96,14 @@ module csrsr (
assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported
assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
assign STATUS_FS = (`S_SUPPORTED && (`F_SUPPORTED || `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
endgenerate
assign STATUS_SD = (STATUS_FS == 2'b11) || (STATUS_XS == 2'b11); // dirty state logic
assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty
always_comb
if (CSRWriteValM[12:11] == `U_MODE && `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
else if (CSRWriteValM[12:11] == `S_MODE && `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
if (CSRWriteValM[12:11] == `U_MODE & `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
else if (CSRWriteValM[12:11] == `S_MODE & `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
else STATUS_MPP_NEXT = `M_MODE;
// registers for STATUS bits

6
wally-pipelined/src/privileged/csru.sv
View File

@ -51,9 +51,9 @@ module csru #(parameter
logic [4:0] NextFFLAGSM;
// Write enables
//assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR) && ~StallW;
assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM | CSRAdrM == FCSR)) && ~StallW;
assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) && ~StallW;
//assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & ~StallW;
assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & ~StallW;
assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & ~StallW;
// Write Values
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];

6
wally-pipelined/src/privileged/trap.sv
View File

@ -62,8 +62,8 @@ module trap (
// interrupt if any sources are pending
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
assign InterruptM = PendingInterruptM & ~CommittedM;
@ -106,7 +106,7 @@ module trap (
generate
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00};
else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};

4
wally-pipelined/src/uncore/uartPC16550D.sv
View File

@ -211,7 +211,7 @@ module uartPC16550D(
if (~HRESETn) begin
baudcount <= #1 1;
baudpulse <= #1 0;
end else if (~MEMWb & DLAB & (A == 3'b0 || A == 3'b1)) begin
end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin
baudcount <= #1 1;
end else begin
// the baudpulse is too long by 2 clock cycles.
@ -248,7 +248,7 @@ module uartPC16550D(
rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter
if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1;
if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle
end else if (rxstate == UART_DONE || rxstate == UART_BREAK) begin
end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin
if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK;
else rxstate <= #1 UART_IDLE;
end

14
wally-pipelined/srt/srt.sv
View File

@ -106,17 +106,17 @@ module qsel(input logic [55:52] ps, pc,
assign #1 magnitude = ~(&p[54:52]);
assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
assign #1 sign = p[55] ^ cout;
/* assign #1 magnitude = ~((ps[54]^pc[54]) && (ps[53]^pc[53]) &&
/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
(ps[52]^pc[52]));
assign #1 sign = (ps[55]^pc[55])^
(ps[54] && pc[54] || ((ps[54]^pc[54]) &&
(ps[53]&&pc[53] || ((ps[53]^pc[53]) &&
(ps[52]&&pc[52]))))); */
(ps[54] & pc[54] | ((ps[54]^pc[54]) &
(ps[53]&pc[53] | ((ps[53]^pc[53]) &
(ps[52]&pc[52]))))); */
// Produce quotient = +1, 0, or -1
assign #1 qp = magnitude && ~sign;
assign #1 qp = magnitude & ~sign;
assign #1 qz = ~magnitude;
assign #1 qm = magnitude && sign;
assign #1 qm = magnitude & sign;
endmodule
//////////
@ -243,7 +243,7 @@ module counter(input logic clk,
always @(posedge clk)
begin
if (count == 54) done <= #1 1;
else if (done || req) done <= #1 0;
else if (done | req) done <= #1 0;
if (req) count <= #1 0;
else count <= #1 count+1;
end

154
wally-pipelined/testbench/common/instrNameDecTB.sv
View File

@ -28,7 +28,7 @@ module instrNameDecTB(
10'b0000011_100: name = "LBU";
10'b0000011_101: name = "LHU";
10'b0000011_110: name = "LWU";
10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
10'b0010011_000: if (instr[31:15] == 0 & instr[11:7] ==0) name = "NOP/FLUSH";
else name = "ADDI";
10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
else name = "ILLEGAL";
@ -147,28 +147,28 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W";
else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X";
else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
else if (funct7[6:2] == 5'b00101) name = "FMIN";
else if (funct7[6:2] == 5'b10100) name = "FLE";
@ -178,24 +178,24 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
else if (funct7[6:2] == 5'b00101) name = "FMAX";
else if (funct7[6:2] == 5'b10100) name = "FLT";
@ -206,24 +206,24 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
else if (funct7[6:2] == 5'b10100) name = "FEQ";
else name = "ILLEGAL";
@ -232,24 +232,24 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
else name = "ILLEGAL";
10'b0000111_010: name = "FLW";
10'b0100111_010: name = "FSW";

2
wally-pipelined/testbench/common/logging.sv
View File

@ -4,7 +4,7 @@ module logging(
input logic [1:0] HTRANS);
always @(posedge clk)
if (HTRANS != 2'b00 && HADDR == 0)
if (HTRANS != 2'b00 & HADDR == 0)
$display("%t Warning: access to memory address 0\n", $realtime);
endmodule

2
wally-pipelined/testbench/common/sdModel.sv
View File

@ -387,7 +387,7 @@ module sdModel
next_datastate = 0;
case(dataState)
DATA_IDLE: begin
if ((CardStatus[12:9]==`RCV) || (mult_write == 1'b1) )
if ((CardStatus[12:9]==`RCV) | (mult_write == 1'b1) )
next_datastate = READ_WAITS;
else if ((CardStatus[12:9]==`DATAS )|| (mult_read == 1'b1) )
next_datastate = WRITE_DATA;

38
wally-pipelined/testbench/testbench-fpga.sv
View File

@ -661,10 +661,10 @@ string tests32f[] = '{
always @(negedge clk)
begin
/* -----\/----- EXCLUDED -----\/-----
if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 |
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1))) begin
-----/\----- EXCLUDED -----/\----- */
if (DCacheFlushDone) begin
@ -703,9 +703,9 @@ string tests32f[] = '{
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
if (signature[i] !== ram.RAM[testadr+i] &&
if (signature[i] !== ram.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
// report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now
errors = errors+1;
@ -751,10 +751,10 @@ string tests32f[] = '{
end
-----/\----- EXCLUDED -----/\----- */
assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 |
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1));
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
@ -779,20 +779,20 @@ endmodule
module riscvassertions();
// Legal number of PMP entries are 0, 16, or 64
initial begin
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
@ -862,7 +862,7 @@ module DCacheFlushFSM
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
for(k = 0; k < numwords; k++) begin
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
end
end

6
wally-pipelined/testbench/testbench-linux.sv
View File

@ -222,7 +222,7 @@ module testbench();
`define checkEQ(NAME, VAL, EXPECTED) \
if(VAL != EXPECTED) begin \
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
end
///////////////////////////////////////////////////////////////////////////////
@ -571,7 +571,7 @@ module testbench();
// turn on waves
if (InstrCountW == INSTR_WAVEON) $stop;
// end sim
if ((InstrCountW == INSTR_LIMIT) && (INSTR_LIMIT!=0)) $stop;
if ((InstrCountW == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
fault = 0;
if (`DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW)
@ -678,7 +678,7 @@ module testbench();
SvMode = SATP[63];
// Only perform translation if translation is on and the processor is not
// in machine mode
if (SvMode && (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
if (SvMode & (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
BaseAdr = SATP[43:0] << 12;
for (i = 2; i >= 0; i--) begin
PAdr = BaseAdr + (VPN[i] << 3);

4
wally-pipelined/testbench/testbench-privileged.sv
View File

@ -135,8 +135,8 @@ module testbench();
// check results
always @(negedge clk)
begin
if (dut.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
if (dut.hart.priv.EcallFaultM &
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 & dut.hart.ieu.dp.regf.a3 == 3 & dut.hart.ieu.dp.regf.wd3 == 1))) begin
$display("Code ended with ecall with gp = 1");
#60; // give time for instructions in pipeline to finish
// clear signature to prevent contamination from previous tests

54
wally-pipelined/testbench/testbench.sv
View File

@ -244,9 +244,9 @@ logic [3:0] dummy;
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
// *** have to figure out how to exclude shadowram when not using a dcache.
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &&
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
// report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now
errors = errors+1;
@ -304,12 +304,12 @@ logic [3:0] dummy;
assign ecf = 0;
end
endgenerate
assign DCacheFlushStart = ecf &&
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1)) ||
(dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423 || dut.hart.ifu.InstrM == 32'hfc32a823) && dut.hart.ieu.c.InstrValidM;
assign DCacheFlushStart = ecf &
(dut.hart.ieu.dp.regf.rf[3] == 1 |
(dut.hart.ieu.dp.regf.we3 &
dut.hart.ieu.dp.regf.a3 == 3 &
dut.hart.ieu.dp.regf.wd3 == 1)) |
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
// **** Fix when the check in the shadow ram is fixed.
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
@ -333,27 +333,27 @@ endmodule
module riscvassertions;
initial begin
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`S_SUPPORTED || `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
assert (`DIV_BITSPERCYCLE == 1 || `DIV_BITSPERCYCLE==2 || `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS || `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS || `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS | `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS | `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
end
endmodule
@ -420,7 +420,7 @@ module DCacheFlushFSM
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
for(k = 0; k < numwords; k++) begin
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
end
end