forked from Github_Repos/cvw
Removed .* from CSRs
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@ -112,13 +112,49 @@ module csr #(parameter
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assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
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assign CSRUWriteM = CSRWriteM;
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csri csri(.*);
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csrsr csrsr(.*);
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csrc counters(.*);
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csrm csrm(.*); // Machine Mode CSRs
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csrs csrs(.*);
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csrn csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers
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csru csru(.*); // Floating Point Flags are part of User MOde
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csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
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.CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
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.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
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csrsr csrsr(.clk, .reset, .StallW,
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.WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM,
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.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
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.mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
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.MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);
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csrc counters(.clk, .reset,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.InstrValidM, .LoadStallD, .CSRMWriteM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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csrm csrm(.clk, .reset, .StallW,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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csrs csrs(.clk, .reset, .StallW,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
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.SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
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.SATP_REGW, .SIP_REGW, .SIE_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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csrn csrn(.clk, .reset, .StallW,
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.CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW,
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.CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW,
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.UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
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csru csru(.clk, .reset, .StallW,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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// merge CSR Reads
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assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;
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@ -153,7 +153,6 @@ module privileged (
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///////////////////////////////////////////
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// Control and Status Registers
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///////////////////////////////////////////
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//csr csr(.*);
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csr csr(.clk, .reset,
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.FlushE, .FlushM, .FlushW,
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.StallE, .StallM, .StallW,
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@ -216,7 +215,6 @@ module privileged (
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
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// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
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//trap trap(.*);
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trap trap(.clk, .reset,
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.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
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