James E. Stine
|
ddbdd0d5a2
|
Modify muldiv.sv to handle W instructions for 64-bits
|
2021-05-31 23:27:42 -04:00 |
|
bbracker
|
39ae743543
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
|
Katherine Parry
|
778ba6bbf5
|
classify unit created and passes imperas tests
|
2021-05-27 18:53:55 -04:00 |
|
Katherine Parry
|
1459d840ed
|
All compare instructions pass imperas tests
|
2021-05-27 15:23:28 -04:00 |
|
Katherine Parry
|
309e6c3dc1
|
FADD and FSUB imperas tests pass
|
2021-05-26 12:33:33 -04:00 |
|
Kip Macsai-Goren
|
8ae43a15d4
|
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
|
2021-05-24 20:59:26 -04:00 |
|
James E. Stine
|
295263e122
|
Mod for DIV/REM instruction and update to div.sv unit
|
2021-05-24 19:29:13 -05:00 |
|
Ross Thompson
|
c5310e85c1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-24 14:28:41 -05:00 |
|
Katherine Parry
|
90d5fdba04
|
FMV.X.D imperas test passes
|
2021-05-24 14:44:30 -04:00 |
|
Ross Thompson
|
8bf411c640
|
Updated branch predictor tests/benchmarks.
|
2021-05-24 11:13:33 -05:00 |
|
Katherine Parry
|
70968a4ec3
|
FSD and FLD imperas tests pass
|
2021-05-23 18:33:14 -04:00 |
|
bbracker
|
846553ac7d
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
James E. Stine
|
e70136ec78
|
Minor testbench updates to rv64icfd
|
2021-05-21 09:41:21 -05:00 |
|
James E. Stine
|
23769e36a5
|
Update to testbench-imperase for rv64icfd
|
2021-05-21 09:28:44 -05:00 |
|
James E. Stine
|
fed3b30557
|
Update to FLD/FSD testbench
|
2021-05-21 09:26:55 -05:00 |
|
James E. Stine
|
c89d3e01bb
|
Update to rv64icfd wally-config to run through FP tests
|
2021-05-21 09:22:17 -05:00 |
|
Katherine Parry
|
4db7f3065c
|
FMV.D.X imperas test passes
|
2021-05-20 22:18:33 -04:00 |
|
Katherine Parry
|
06af239e6c
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
|
bbracker
|
1d3db5ead5
|
small bit of busybear debug progress
|
2021-05-19 20:18:00 -04:00 |
|
bbracker
|
979a9bf037
|
commented out MSTATUS test
|
2021-05-19 12:38:01 -04:00 |
|
James E. Stine
|
44dc665fc5
|
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
|
2021-05-18 13:48:44 -05:00 |
|
David Harris
|
26531f2634
|
fixed rv64mmu makefile
|
2021-05-18 14:25:55 -04:00 |
|
Katherine Parry
|
9464c9022d
|
floating point infinite loop removed from imperas tests
|
2021-05-18 10:42:51 -04:00 |
|
bbracker
|
f00eb22700
|
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
|
2021-05-17 19:25:54 -04:00 |
|
bbracker
|
e4c90f503a
|
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
|
2021-05-17 18:44:47 -04:00 |
|
James E. Stine
|
daf780b9c2
|
Mod Imperas Testbench for updated Div/Rem
|
2021-05-17 16:56:30 -05:00 |
|
Domenico Ottolia
|
88ab07d456
|
Forgot to add csr permission tests to testbench
|
2021-05-04 20:20:22 -04:00 |
|
ushakya22
|
682bc7b58e
|
Added mip tests to testbench
|
2021-05-04 15:36:06 -04:00 |
|
Domenico Ottolia
|
8398e653dd
|
Re-add medeleg tests to testbench
|
2021-05-04 14:42:20 -04:00 |
|
ushakya22
|
46f20745d7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 02:22:17 -04:00 |
|
ushakya22
|
b805b98a8c
|
Added MIE tests to testbench
|
2021-05-04 02:22:01 -04:00 |
|
Domenico Ottolia
|
1673ad6e27
|
Minor tweaks to mcause & scause tests
|
2021-05-04 01:33:49 -04:00 |
|
David Harris
|
45b0af497c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 01:19:57 -04:00 |
|
David Harris
|
d68fe44446
|
Fixed testbench to produce error when signature.output doesn't exist
|
2021-05-04 01:19:44 -04:00 |
|
Thomas Fleming
|
41a19153cc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-04 01:14:13 -04:00 |
|
Domenico Ottolia
|
67c7bfe34d
|
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
|
2021-05-04 01:04:12 -04:00 |
|
Domenico Ottolia
|
973f32da47
|
Fix 32 bit privileged tests!!!
|
2021-05-04 00:16:19 -04:00 |
|
Thomas Fleming
|
a3b5ae9742
|
Restore original order of tests
|
2021-05-03 23:50:21 -04:00 |
|
Thomas Fleming
|
ad40464557
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-03 23:15:39 -04:00 |
|
Thomas Fleming
|
803a69efe6
|
Enable mmu tests in testbench
|
2021-05-03 23:15:23 -04:00 |
|
Domenico Ottolia
|
2669a6a0db
|
Run all tests
|
2021-05-03 22:38:59 -04:00 |
|
Domenico Ottolia
|
4d70e22a6a
|
Update cause tests to be longer
|
2021-05-03 22:38:26 -04:00 |
|
Domenico Ottolia
|
997c9ad5c0
|
Add mtvec and stvec tests to testbench
|
2021-05-03 22:19:50 -04:00 |
|
Shriya Nadgauda
|
780ad3eaf4
|
working testbench-imperas
|
2021-05-03 22:16:58 -04:00 |
|
Shriya Nadgauda
|
c5a306426a
|
finishing merge conflict changes
|
2021-05-03 22:15:05 -04:00 |
|
Shriya Nadgauda
|
b7159652f6
|
merge conflict fixes
|
2021-05-03 22:12:30 -04:00 |
|
Shriya Nadgauda
|
968994c04a
|
updated pipeline tests
|
2021-05-03 22:07:36 -04:00 |
|
Elizabeth Hedenberg
|
2d1d929485
|
coremark print statment
|
2021-05-03 19:35:08 -04:00 |
|
Elizabeth Hedenberg
|
2a33673e3c
|
coremark updates
|
2021-05-03 19:35:07 -04:00 |
|
Elizabeth Hedenberg
|
463ba1a2be
|
coremark directory changes
|
2021-05-03 19:35:06 -04:00 |
|
David Harris
|
d7438929d4
|
Extended maximum signature length to 1M
|
2021-05-03 15:29:20 -04:00 |
|
bbracker
|
2368b58cc9
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-03 09:23:52 -04:00 |
|
Noah Boorstin
|
b32128465c
|
busybear: remove now unneeded hack for fixed CSR issue
|
2021-05-01 15:17:04 -04:00 |
|
Katherine Parry
|
db95151d8d
|
fpu imperas tests run
|
2021-05-01 02:18:01 +00:00 |
|
bbracker
|
1fcd43e844
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-30 06:26:35 -04:00 |
|
bbracker
|
182bfdbb0e
|
rv32 plic test and lint fixes
|
2021-04-30 06:26:31 -04:00 |
|
Domenico Ottolia
|
d03ca20dc9
|
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
|
2021-04-29 20:42:14 -04:00 |
|
Ross Thompson
|
818c0abc89
|
Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
|
2021-04-29 17:36:46 -05:00 |
|
Domenico Ottolia
|
c60c4f4adc
|
Minor improvements to scause test
|
2021-04-29 16:48:07 -04:00 |
|
Domenico Ottolia
|
c8a81779ca
|
Add machine-mode timer interrupts to mcause tests
|
2021-04-29 16:39:18 -04:00 |
|
Domenico Ottolia
|
6fc04768f5
|
Same but don't break sim-wally this time
|
2021-04-29 15:33:27 -04:00 |
|
Domenico Ottolia
|
7ae5d4d11e
|
Add more exceptions to medeleg tests
|
2021-04-29 15:32:13 -04:00 |
|
ushakya22
|
77210527c1
|
Working MIE timer tests
|
2021-04-29 15:19:43 -04:00 |
|
Domenico Ottolia
|
4fae8088e3
|
Add medeleg tests
|
2021-04-29 15:02:36 -04:00 |
|
Noah Boorstin
|
a4dad3403e
|
same but do that right this time
|
2021-04-28 14:27:28 -04:00 |
|
Noah Boorstin
|
44606b6c19
|
busybear: respect branch predictor disable config
|
2021-04-27 15:52:18 -04:00 |
|
Ross Thompson
|
8ae28e7887
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-26 14:28:09 -05:00 |
|
Ross Thompson
|
72363f5c66
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
Noah Boorstin
|
ff1a6b63ed
|
ok but do that better
|
2021-04-26 14:38:05 -04:00 |
|
Noah Boorstin
|
0324329ed9
|
linux: start using internal branch predictor signal
|
2021-04-26 14:34:38 -04:00 |
|
Noah Boorstin
|
ee628e388a
|
minor busybear fixes
|
2021-04-26 13:24:39 -04:00 |
|
Ross Thompson
|
8e5409af66
|
Icache integrated!
Merge branch 'icache-almost-working' into main
|
2021-04-26 11:48:58 -05:00 |
|
bbracker
|
31a0387136
|
merge cleanup; mem init is broken
|
2021-04-26 08:00:17 -04:00 |
|
bbracker
|
ba94fa3436
|
it says I need to merge in order to pull
|
2021-04-26 07:46:24 -04:00 |
|
bbracker
|
1cc0dcc83f
|
progress on bus and lrsc
|
2021-04-26 07:43:16 -04:00 |
|
Ross Thompson
|
6e803b724e
|
Merge branch 'tests' into icache-almost-working
|
2021-04-25 21:25:36 -05:00 |
|
bbracker
|
86946266cf
|
thomas fixed it before I did
|
2021-04-24 09:38:52 -04:00 |
|
bbracker
|
a3487a9e47
|
do script refactor
|
2021-04-24 09:32:09 -04:00 |
|
Thomas Fleming
|
e3672ca23f
|
Add address translation to busybear testbench
|
2021-04-23 20:12:20 -04:00 |
|
Noah Boorstin
|
09755251bc
|
busybear
|
2021-04-23 17:32:37 -04:00 |
|
Shriya Nadgauda
|
c66e63ff70
|
adding pipeline testing
|
2021-04-23 14:19:17 -04:00 |
|
Ross Thompson
|
020fb65adf
|
Fixed icache for 32 bit.
Merge branch 'cache' into main
|
2021-04-22 16:45:29 -05:00 |
|
Thomas Fleming
|
6acaa313b5
|
Temporarily disable rv64 mmu test
Will restore once cache revamp is pushed
|
2021-04-22 13:19:18 -04:00 |
|
Noah Boorstin
|
cd7ea29ce6
|
buildroot: add workaround for weird initial MSTATUS state
|
2021-04-21 16:03:42 -04:00 |
|
Domenico Ottolia
|
44da1488ff
|
Add tests for stval and mtval
|
2021-04-21 02:31:32 -04:00 |
|
Domenico Ottolia
|
f63f16f486
|
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
|
2021-04-21 01:12:55 -04:00 |
|
Domenico Ottolia
|
bf86a809eb
|
Add tests for sepc register
|
2021-04-20 23:50:53 -04:00 |
|
Ross Thompson
|
251ece20fe
|
Broken icache. Design is done. Time to debug.
|
2021-04-20 19:55:49 -05:00 |
|
Noah Boorstin
|
3f0ead9d4e
|
yay buildroot passes a decent amount of tests now
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
|
2021-04-19 03:26:08 -04:00 |
|
Jarred Allen
|
850f728cc7
|
Merge branch 'main' into cache
|
2021-04-19 00:05:23 -04:00 |
|
Noah Boorstin
|
2af4e2f4ac
|
slowly more buildroot progress
|
2021-04-18 18:18:07 -04:00 |
|
Noah Boorstin
|
9bb1233433
|
neat verilog thing
|
2021-04-18 17:48:51 -04:00 |
|
Noah Boorstin
|
6954e6df4c
|
buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
|
2021-04-17 14:44:32 -04:00 |
|
Noah Boorstin
|
4f97e9e761
|
start to add buildroot testbench
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
|
2021-04-16 23:27:29 -04:00 |
|
bbracker
|
290b3424e5
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-15 21:09:27 -04:00 |
|
bbracker
|
368c94d4ff
|
working GPIO interrupt demo
|
2021-04-15 21:09:15 -04:00 |
|
Domenico Ottolia
|
9f13ee3f31
|
Add tests for scause and ucause
|
2021-04-15 19:41:25 -04:00 |
|
Domenico Ottolia
|
531423d7e1
|
Add 32 bit privileged tests
|
2021-04-15 16:55:39 -04:00 |
|
Jarred Allen
|
81c02bda55
|
Merge branch 'main' into cache
|
2021-04-15 13:47:19 -04:00 |
|
Thomas Fleming
|
3c49fd08f6
|
Remove imem from testbenches
|
2021-04-14 20:20:34 -04:00 |
|