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1519 Commits

Author SHA1 Message Date
Ross Thompson
cfd522da6b The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
0b1e59d075 Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
a158558b83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
ff5379fd95 fix regression 2021-09-15 17:30:59 -04:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
bbracker
ee1503a249 created script to determine which functions are most frequently used 2021-09-14 19:41:05 -04:00
David Harris
92385a1d51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
cd6d1e0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
7be1160a48 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
bbb6c7bef7 Restored old integer divider 2021-09-12 22:07:52 -04:00
Ross Thompson
296da4f437 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
dd1e7548ed Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
be864abcc5 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
570aab4275 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
5744796431 Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f fixed some lint bugs. 2021-09-09 12:38:57 -05:00
bbracker
4a17af5b7c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-09 13:22:31 -04:00
bbracker
3a520cb540 changed fix_mem to not use hardcoded file names 2021-09-09 13:22:24 -04:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
86fbe2a654 Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
a15d6c1c96 Slight modification to wave file. 2021-09-08 10:40:46 -05:00
bbracker
bb84354a47 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
f8272c45d1 make testbench successfully deactivate TimerIntM so as to create a nice pulse 2021-09-07 15:36:47 -04:00
Ross Thompson
49e75d579c Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
bbracker
da9a366d20 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
Ross Thompson
05455f8392 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
bbracker
502ddb3bb5 help in case a script is run accidentally 2021-09-06 16:23:45 -04:00
bbracker
b3bc3cf6d0 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
bbracker
c463f177e9 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
bbracker
135404174e switching over to hopefully more consistent QEMU simulated clock 2021-09-04 19:43:39 -04:00
bbracker
9fde9f09f2 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing 2021-09-04 19:41:55 -04:00
James E. Stine
02a1fda650 Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
bbracker
f1a39b467d output trace to linux-testvectors folder 2021-09-01 17:37:46 -04:00
Ross Thompson
2968623f9a Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
70f332fe2f FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
6a9fa2fae3 Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
d433db3048 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785 Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6 Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6 Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790 Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
fd28c4f556 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
e4bbd3bbc7 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
91fba80a6d Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
8836d91896 Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
596bc138bc Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
0530047f53 Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
c5e2443298 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
e5336f4ee1 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
2ccf479354 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
35e57a7c61 partial dcache reorg. 2021-08-25 12:42:05 -05:00
Ross Thompson
983524e81b Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00
David Harris
7d24ed3c51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
3fa55a01f4 simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
fe378f2692 Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
0cc47f3daf Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
9fdcc6c9ca Renamed output of qemu trace. 2021-08-22 22:56:34 -05:00
Ross Thompson
2825074114 Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
4677b4bb38 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
ddbc659d7b Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
Ross Thompson
65870877c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
91b51c698e Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
c8847b27e8 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
a70d51f4c9 Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
36761d9155 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
6c57002d0e Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
af2c6fd6ff Updated linux-wave.do to have cursors at the timer interrupt problem. 2021-08-13 17:29:37 -05:00
Ross Thompson
766c829d31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Katherine Parry
aedd71d570 move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
6a6d5e9b15 Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
814fd80b0f Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
9ff9c4dff9 Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00
Ross Thompson
565c01709d Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
2be625d8b9 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
4b25fed6d8 Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
22f274c51e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
67c1028862 Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
cce0571925 Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
d3be04b7de Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
aa9a5d879b Finally past the CLINT issues. 2021-08-06 16:41:34 -05:00
Ross Thompson
0bfbcef8ab Now past the CLINT issues. 2021-08-06 16:16:39 -05:00