Ross Thompson ddbc659d7b Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.		2021-08-19 10:33:11 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
linux-testgen	Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.	2021-08-05 16:49:03 -05:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.	2021-08-19 10:33:11 -05:00
src	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-08-17 16:06:54 -05:00
testbench	Added logic to linux test bench to not stop simulation on csr write faults.	2021-08-15 11:13:32 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00