Ross Thompson d23b860c96 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. ... This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.		2021-08-25 21:09:42 -05:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
linux-testgen	Updated linux test bench documenation and scripts.	2021-08-25 10:54:47 -05:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.	2021-08-25 21:09:42 -05:00
src	Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.	2021-08-25 21:09:42 -05:00
testbench	Removed generate around the dcache memories.	2021-08-25 13:27:26 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00