forked from Github_Repos/cvw
Third attempt at fixing the write enables for the icache cacheway.
This commit is contained in:
parent
6965bde95c
commit
6f4542f063
2
wally-pipelined/src/cache/icache.sv
vendored
2
wally-pipelined/src/cache/icache.sv
vendored
@ -142,7 +142,7 @@ module icache
|
||||
.RAdr(RAdr),
|
||||
.PAdr(PCTagF),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.WriteWordEnable({NUMWAYS{1'b1}}),
|
||||
.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
|
||||
.TagWriteEnable(SRAMWayWriteEnable),
|
||||
.WriteData(ICacheMemWriteData),
|
||||
.SetValid(ICacheMemWriteEnable),
|
||||
|
Loading…
Reference in New Issue
Block a user