cvw/wally-pipelined
Ross Thompson 96cbd8e785 Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
..
bin
config move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
fpu-testfloat/FMA/tbgen move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
linux-testgen Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00
misc
ppa
regression Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 2021-08-27 11:03:36 -05:00
src Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 2021-08-27 11:03:36 -05:00
testbench Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
testgen mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
lint-wally