Ross Thompson 4b25fed6d8 Simplified Dcache by sharing the read data mux with the victim selection mux.		2021-08-11 16:55:55 -05:00
..
bin
config	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
fpu-testfloat/FMA/tbgen	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
linux-testgen	Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.	2021-08-05 16:49:03 -05:00
misc
ppa
regression	Fixed another bug with the atomic instrucitons implemention in the dcache.	2021-08-08 22:50:31 -05:00
src	Simplified Dcache by sharing the read data mux with the victim selection mux.	2021-08-11 16:55:55 -05:00
testbench	Fixed another bug with the atomic instrucitons implemention in the dcache.	2021-08-08 22:50:31 -05:00
testgen
lint-wally