Ross Thompson fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. ... Fixed logic for trace update in the M and W stages. The M stage should not update if there is an instruction fault.		2021-08-08 00:28:18 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
fpu-testfloat/FMA/tbgen	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
linux-testgen	Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.	2021-08-05 16:49:03 -05:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.	2021-08-08 00:28:18 -05:00
src	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.	2021-08-08 00:28:18 -05:00
testbench	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.	2021-08-08 00:28:18 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00