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The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.

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Ross Thompson 2021-09-17 10:33:57 -05:00
parent 0b1e59d075
commit cfd522da6b
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/hazard/hazard.sv
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@ -78,7 +78,7 @@ module hazard(
assign FlushF = BPPredWrongE | InvalidateICacheM;
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
assign FlushM = FirstUnstalledM | TrapM | RetM;
assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM;
// on Trap the memory stage should be flushed going into the W stage,
// except if the instruction causing the Trap is an ecall or ebreak.
assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));