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461 Commits

Author SHA1 Message Date
Ross Thompson
f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69 Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
0932d4df46 Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
6e16922aae WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010 Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
de868ef3a2 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Ross Thompson
900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
David Harris
fb95767da0 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
3db60a1cc1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
48c49802b2 Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
301f20052b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
e09079d8b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
55df8bc3f7 fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
da93d14050 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
b5cdf035fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
ade4a4cd5e Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
bdb3417656 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
0f7e995055 simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
c7043e4d63 Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
88c5cdc873 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2 Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
54001222cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
285fc6fd4d Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
dd3af17b3f Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
3457c6e512 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
69a0f6e00b big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
9b1f85d353 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
Ross Thompson
e4f4e1bd43 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
David Harris
03fa9084bc Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
bbracker
8ea25e591b fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
709f8e6e0d fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Ross Thompson
61c714ebe6 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
fe896bff8e Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
d33de3ef6b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
4b376e2834 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
7cf994526a fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Katherine Parry
fcd23a006e fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
849707f161 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
b2487f4b72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Katherine Parry
23adb2dd03 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
ca8fb45367 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
ee4b38dce3 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
67ff8f27f4 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
654c4d1148 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36 Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
bc2b757952 bit write update 2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
89e0830883 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
00908132e6 Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
c8f2dce026 fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
David Harris
7391c6d338 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
8e83aaeced fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
11423d1d17 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
6d7bc928af update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
David Harris
c543fedc60 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
David Harris
0ecfff7e3a FMA project ready to start 2022-03-01 20:58:08 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
2ea93c4ac3 adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
2de31a15da Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9 hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
f4be78ecc3 Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
3675a813c6 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
62d62f9a9e Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
c35a071203 Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
283a25e1a7 fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
40bc380073 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
f29cc4b33f simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
b2db58e982 Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
a9f9cfa5b6 Added start of fma 2022-02-26 19:51:19 +00:00
Ross Thompson
730fdb029a Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
c26526c9f3 change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Ross Thompson
a60332b455 Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
4e194b2576 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7 Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
3036de316a Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01 cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791 Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
799736632b Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00