Noah Limpert
70a84b56c8
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Noah Limpert
27251a9935
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
David Harris
2bf51362e2
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
4bf823e063
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
d570df864f
IEU lint cleanup
2021-10-23 10:51:53 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
33358d101e
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
David Harris
ceaf84a3ce
removed .* from wallypipeliendsoc
2021-10-20 13:49:18 -07:00
David Harris
b3bded9e6c
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
8836d91896
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
0cc47f3daf
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
David Harris
2f81e4c70d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
863e6e72d6
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
a855e0170e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
David Harris
b65788d165
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
David Harris
a898bbb991
Removed rest of HRDATAW from ahblite
2021-07-17 02:15:24 -04:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
8610ef204c
Renamed DCacheStall to LSUStall in hart and hazard.
...
Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Katherine Parry
f5bfdf46db
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
f4295ff097
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
...
This solves the committedM issue.
2021-07-14 15:00:33 -05:00
Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
afc1bc9c38
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
Ross Thompson
47e16f5629
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
Katherine Parry
ca19b2e215
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
David Harris
600e7802dd
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 18:56:30 -04:00
Ross Thompson
7f62808544
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
Ross Thompson
5b70eb86b0
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
2021-07-04 13:49:38 -05:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
Ross Thompson
9f16d08d0d
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
Ross Thompson
043f1e10c5
Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
2021-07-03 15:51:25 -05:00
Ross Thompson
7b3716c281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
Ross Thompson
dbd33465e1
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
David Harris
5b6ebd7935
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:52:20 -04:00
David Harris
c85e0df1ff
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
118dfa9cec
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
17afd9e5e8
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
