Added performance counters for dcache access and dcache miss.

wally-pipelined/src/cache/dcache.sv

@@ -46,6 +46,8 @@ module dcache
    output logic [`XLEN-1:0]    ReadDataM, 
    output logic 	       DCacheStall,
    output logic 	       CommittedM,
+   output logic 	       DCacheMiss,
+   output logic 	       DCacheAccess,
 
    // inputs from TLB and PMA/P
    input logic 		       ExceptionM,
@@ -53,7 +55,7 @@ module dcache
    input logic 		       DTLBMissM,
    input logic 		       CacheableM,
    input logic 		       DTLBWriteM,
-   input logic 		       ITLBWriteF,   
+   input logic 		       ITLBWriteF, 
    // from ptw
    input logic 		       SelPTW,
    input logic 		       WalkerPageFaultM, 
@@ -416,7 +418,7 @@ module dcache
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;
 
-
+  
   // next state logic and some state ouputs.
   always_comb begin
     DCacheStall = 1'b0;
@@ -437,6 +439,8 @@ module dcache
     CommittedM = 1'b0;        
     SelUncached = 1'b0;
     SelEvict = 1'b0;
+    DCacheAccess = 1'b0;
+    DCacheMiss = 1'b0;
 
     case (CurrState)
       STATE_READY: begin
@@ -472,7 +476,8 @@ module dcache
 	// read hit valid cached
 	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  DCacheStall = 1'b0;
-
+	  DCacheAccess = 1'b1;
+	  
 	  if(StallW) begin
 	    NextState = STATE_CPU_BUSY;
             SelAdrM = 1'b1;
@@ -485,6 +490,7 @@ module dcache
 	  DCacheStall = 1'b0;
 	  SRAMWordWriteEnableM = 1'b1;
 	  SetDirtyM = 1'b1;
+	  DCacheStall = 1'b1;
 	  
 	  if(StallW) begin 
 	    NextState = STATE_CPU_BUSY;
@@ -497,6 +503,8 @@ module dcache
 	  NextState = STATE_MISS_FETCH_WDV;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
+	  DCacheAccess = 1'b1;
+	  DCacheMiss = 1'b1;
 	end
 	// uncached write
 	else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin

wally-pipelined/src/lsu/lsu.sv

@@ -45,6 +45,8 @@ module lsu
    output logic 	       CommittedM, 
    output logic 	       SquashSCW,
    output logic 	       DataMisalignedM,
+   output logic 	       DCacheMiss,
+   output logic 	       DCacheAccess,
 
    // address and write data
    input logic [`XLEN-1:0]     MemAdrM,
@@ -315,6 +317,8 @@ module lsu
 		.ReadDataM(HPTWReadPTE),
 		.DCacheStall(DCacheStall),
 		.CommittedM(CommittedMfromDCache),
+		.DCacheMiss,
+		.DCacheAccess,		
 		.ExceptionM(ExceptionM),
 		.PendingInterruptM(PendingInterruptMtoDCache),
 		.DTLBMissM(DTLBMissM),

wally-pipelined/src/privileged/csr.sv

@@ -46,6 +46,8 @@ module csr #(parameter
   input  logic 		   RASPredPCWrongM,
   input  logic 		   BPPredClassNonCFIWrongM,
   input  logic [4:0]       InstrClassM,
+  input  logic             DCacheMiss,
+  input  logic             DCacheAccess,
   input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
   input  logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
   input  logic             BreakpointFaultM, EcallFaultM,

wally-pipelined/src/privileged/csrc.sv

@@ -78,6 +78,8 @@ module csrc #(parameter
     input  logic             RASPredPCWrongM,
     input  logic             BPPredClassNonCFIWrongM,
     input  logic [4:0]       InstrClassM,
+    input  logic             DCacheMiss,
+    input  logic             DCacheAccess,
     input  logic [11:0]      CSRAdrM,
     input  logic [1:0]       PrivilegeModeW,
     input  logic [`XLEN-1:0] CSRWriteValM,
@@ -143,7 +145,9 @@ module csrc #(parameter
         assign CounterEvent[8] = RASPredPCWrongM & ~StallM;
         assign CounterEvent[9] = InstrClassM[3] & ~StallM;
         assign CounterEvent[10] = BPPredClassNonCFIWrongM & ~StallM;
-        assign CounterEvent[`COUNTERS-1:11] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+        assign CounterEvent[11] = DCacheAccess & ~StallM;
+        assign CounterEvent[12] = DCacheMiss & ~StallM;      
+        assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
 
         for (i = 3; i < `COUNTERS; i = i+1) begin
             assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);
@@ -509,4 +513,4 @@ module csrc #(parameter
         end // end for else
     endgenerate
 endmodule
-*/
+*/

wally-pipelined/src/privileged/privileged.sv

@@ -45,6 +45,8 @@ module privileged (
   input  logic 		   RASPredPCWrongM,
   input  logic 		   BPPredClassNonCFIWrongM,
   input  logic [4:0]       InstrClassM,
+  input  logic             DCacheMiss,
+  input  logic             DCacheAccess,
   input  logic             PrivilegedM,
   input  logic             ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
   input  logic             WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM,

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -164,6 +164,8 @@ module wallypipelinedhart
   
   logic 		    ExceptionM;
   logic 		    PendingInterruptM;
+  logic 		    DCacheMiss;
+  logic 		    DCacheAccess;
 
   
   ifu ifu(.InstrInF(InstrRData),
@@ -185,7 +187,9 @@ module wallypipelinedhart
 	  .AtomicM(AtomicM),    
 	  .ExceptionM(ExceptionM),
 	  .PendingInterruptM(PendingInterruptM),		
-	  .CommittedM(CommittedM),          
+	  .CommittedM(CommittedM),
+	  .DCacheMiss,
+          .DCacheAccess,
 	  .SquashSCW(SquashSCW),            
 	  .DataMisalignedM(DataMisalignedM),
 	  .MemAdrE(MemAdrE),