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Commit Graph

103 Commits

Author SHA1 Message Date
David Harris
418e9cd6e6 Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
5db800fac3 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
3a85c972b6 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
5d64f04752 Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
f913305993 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
afd6babc13 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
e33ef58e67 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
4926ae343a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
852eb24731 Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
9d63aa683f Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
fbe6e41169 Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
9d8e7f2714 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
760f4d66dd RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
David Harris
bbb6c7bef7 Restored old integer divider 2021-09-12 22:07:52 -04:00
David Harris
dd1e7548ed Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
36761d9155 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
David Harris
ac163e091c Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
David Harris
b23192cf1b Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
David Harris
accbebfa6f Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
01d6ca1e2a Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
Katherine Parry
0acf665a8b lint is clean 2021-06-07 14:22:54 -04:00
James E. Stine
eba7ce64f5 delete div.bak 2021-06-01 17:39:54 -04:00
James E. Stine
2eeb12c674 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
James E. Stine
ddbdd0d5a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
James E. Stine
46a232b862 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
9954d16fc9 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
12c34c25f3 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
James E. Stine
c4f3f2f783 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
295263e122 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
James E. Stine
e808b06b82 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
James E. Stine
5506efc115 Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
865b3ee219 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
David Harris
a37d9b5e8e Fixed lint error in div 2021-05-03 09:26:12 -04:00
Thomas Fleming
53c05d6a73 Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Teo Ene
ddc98e7d08 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Ross Thompson
35f8b4f74f Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
Ross Thompson
d21006d048 Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6 Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
a16fd95eed Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
David Harris
acd7ba8b60 Updated creation date of mul 2021-02-18 08:13:08 -05:00
David Harris
2f5b4c3a25 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
64536dbc34 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
3edf910c18 Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
cb0054b524 Multiply instructions working 2021-02-17 15:29:20 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00