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Added more pipeline stage suffixes to divider

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This commit is contained in:
David Harris 2021-10-03 00:06:57 -04:00
parent b3bded9e6c
commit 418e9cd6e6
2 changed files with 3 additions and 3 deletions
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4
wally-pipelined/src/muldiv/intdivrestoring.sv
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@ -63,12 +63,12 @@ module intdivrestoring (
// Take absolute value for signed operations
neg #(`XLEN) negd(DSavedE, DnE);
mux2 #(`XLEN) dabsmux(DSavedE, DnE, SignedDivideE & SignDE, Din); // take absolute value for signed operations
mux2 #(`XLEN) dabsmux(DnE, DSavedE, SignedDivideE & SignDE, DAbsB); // take absolute value for signed operations, and negate for subtraction setp
neg #(`XLEN) negx(XSavedE, XnE);
mux2 #(`XLEN) xabsmux(XSavedE, XnE, SignedDivideE & SignXE, Xinit); // need original X as remainder if doing divide by 0
// Negate D for subtraction
assign DAbsB = ~Din;
//assign DAbsB = ~Din;
// *** merge this into dabsmux if possible
// Put suffixes on Xinit, init->DivInitE, Wn, XQn

2
wally-pipelined/src/muldiv/intdivrestoringstep.sv
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@ -33,7 +33,7 @@ module intdivrestoringstep(
logic qi, qib;
assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} /*+ 1*/; // subtractor, carry out determines quotient bit ***replace with add
assign qi = ~qib;
mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
endmodule