Ross Thompson
|
b1475df5e1
|
Wavefile updates.
|
2022-12-22 19:45:02 -06:00 |
|
Ross Thompson
|
41fe876e7a
|
First pass at resolving ifu flush on trap rather than FlushD.
|
2022-12-22 15:53:06 -06:00 |
|
cturek
|
3574bedb08
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-22 05:45:00 +00:00 |
|
cturek
|
80ca75e216
|
Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
|
2022-12-22 05:44:55 +00:00 |
|
David Harris
|
c42967f5c6
|
XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 20:39:38 -08:00 |
|
Ross Thompson
|
c8c73f47d2
|
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
|
2022-12-21 22:13:05 -06:00 |
|
cturek
|
0b4d81bd4a
|
worked out some bugs with int div cycles
|
2022-12-22 02:22:01 +00:00 |
|
cturek
|
c3fdc0ab23
|
Renamed signals to E and M stages, forwarded preprocessed n to fsm
|
2022-12-22 00:43:27 +00:00 |
|
Ross Thompson
|
84f8d9953f
|
Updated cache fsm names to match book.
|
2022-12-21 16:49:53 -06:00 |
|
Ross Thompson
|
d72cf65809
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-21 16:13:09 -06:00 |
|
Ross Thompson
|
e7a44d8975
|
Changed GatedStallF to GatedStallD.
|
2022-12-21 16:12:55 -06:00 |
|
David Harris
|
d0a3e939e3
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 14:12:25 -08:00 |
|
David Harris
|
8bc753a291
|
Added assertion about atomics needing caches
|
2022-12-21 13:57:28 -08:00 |
|
Ross Thompson
|
e5f7e68d31
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-21 14:57:19 -06:00 |
|
Ross Thompson
|
b7224cc5ba
|
Updated fpga constraints.
|
2022-12-21 14:50:01 -06:00 |
|
cturek
|
0c30ecf86d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-21 20:41:38 +00:00 |
|
David Harris
|
6d46261350
|
comment cleanup
|
2022-12-21 12:39:09 -08:00 |
|
David Harris
|
c7f3aae084
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
cturek
|
ab71962dc0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-21 19:35:57 +00:00 |
|
cturek
|
c479b9f112
|
fixed normshift calculations
|
2022-12-21 19:35:47 +00:00 |
|
David Harris
|
5ef3a1d371
|
git push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 11:31:27 -08:00 |
|
David Harris
|
e327d70cdc
|
Removed unused FPU signals
|
2022-12-21 11:31:22 -08:00 |
|
Ross Thompson
|
c3b43b2fac
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
0b4186f1e8
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Ross Thompson
|
91f948a91c
|
The optimzied PC+2/4 logic still hanges on wally32priv.
|
2022-12-21 09:19:34 -06:00 |
|
Ross Thompson
|
6858b7568c
|
Renamed PCPlusUpperF to PCPlus4F.
|
2022-12-21 09:18:30 -06:00 |
|
Ross Thompson
|
3d95aa3423
|
Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
|
2022-12-21 09:18:00 -06:00 |
|
Ross Thompson
|
ac94b55e74
|
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
|
2022-12-21 09:00:09 -06:00 |
|
Ross Thompson
|
a02b40cf02
|
Changes to wave file.
|
2022-12-21 08:41:47 -06:00 |
|
Ross Thompson
|
fe723af1af
|
Comments about PC+2/4.
|
2022-12-21 08:35:43 -06:00 |
|
David Harris
|
5d91b3044f
|
Clean up vecgtored interrupts
|
2022-12-20 16:53:09 -08:00 |
|
David Harris
|
dd0a02f0c8
|
Converted tvecmux to structural
|
2022-12-20 16:24:04 -08:00 |
|
Ross Thompson
|
f860440361
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 18:09:37 -06:00 |
|
Ross Thompson
|
80be2e7be5
|
privileged pc mux cleanup.
|
2022-12-20 18:05:44 -06:00 |
|
Ross Thompson
|
97593e8a6f
|
Moved privileged pc logic into privileged unit.
|
2022-12-20 17:55:45 -06:00 |
|
David Harris
|
8f640f050f
|
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
|
2022-12-20 15:38:30 -08:00 |
|
Ross Thompson
|
35ad49502f
|
Implement FENCE.I as NOP when ZIFENCEI is not supported.
|
2022-12-20 17:34:11 -06:00 |
|
Ross Thompson
|
0dc09ac22d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 17:11:35 -06:00 |
|
Ross Thompson
|
65cbff9283
|
Changed long names of vectored pcm signals.
|
2022-12-20 17:01:20 -06:00 |
|
David Harris
|
f3e9950317
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-20 14:43:33 -08:00 |
|
David Harris
|
e7702e48b7
|
FPU remove unused signals
|
2022-12-20 14:43:30 -08:00 |
|
Ross Thompson
|
6f543d01b7
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 16:36:44 -06:00 |
|
Ross Thompson
|
8029b12f2a
|
Renumbered bits for PCPlusUpper.
|
2022-12-20 16:33:49 -06:00 |
|
David Harris
|
caef1a6997
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-20 11:23:53 -08:00 |
|
David Harris
|
f0ef5caf32
|
Memory cleanup
|
2022-12-20 11:22:26 -08:00 |
|
Ross Thompson
|
c4901450c4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 12:58:59 -06:00 |
|
Ross Thompson
|
684d260005
|
Reorganized IFU PCNextF logic.
|
2022-12-20 12:58:54 -06:00 |
|
David Harris
|
03c700d91c
|
Restored rv32d arch test after new push
|
2022-12-20 10:56:33 -08:00 |
|
David Harris
|
e74d47bcb4
|
Renamed renamed sram to ram
|
2022-12-20 08:36:45 -08:00 |
|
David Harris
|
16f3c25cb7
|
sram1p1rw cleanup
|
2022-12-20 02:57:51 -08:00 |
|