Commit Graph

450 Commits

Author SHA1 Message Date
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
23194c0308 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
4e96d0f1db add checkpoints to regression 2021-11-20 19:42:53 -08:00
bbracker
e5d3416258 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-19 20:25:06 -08:00
bbracker
713aa7faac automatic bug finder script 2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8 increase buildroot progress expecttions; increase timeout to 20 hours 2021-11-19 12:52:11 -08:00
David Harris
402b473dbb CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
0a281a06e0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Kevin Kim
6437c04074 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
David Harris
c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
Ross Thompson
7497422667 Changed several things.
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
Kevin Kim
7cb8b76ef6 Makefile added in regression directory:
-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
f6a555009b increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
0c7681b942 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
David Harris
d7f0abca5a Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
60573b92b2 Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
fe2cda493c fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
5783e47e1a Changes for floating point sims 2021-10-27 10:37:35 -07:00
David Harris
b7b6d6f23f removed unused signal from wave.do 2021-10-26 09:02:22 -07:00
bbracker
66e53929ce adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
Ross Thompson
81054d9168 Fixed issue with dtim (fpga) external abhlite select not triggering.
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
32f0b97cd3 Updated uncore to use sdc.
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
13763b002a switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
c0a7b12f94 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
e0b6566cbd buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
200eb453fb wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
ac1b1bfbb6 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
d11136c406 Fixed bug with the external memory region selection.
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
bfe633d087 Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
bbracker
13352eccda Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00