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old
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Divider FSM simplification
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2021-10-10 22:24:14 -07:00 |
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slack-notifier
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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wave-dos
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Removed negedge flops from divider
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2021-10-10 10:41:13 -07:00 |
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fpga-wave.do
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Fixed bug with the external memory region selection.
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2021-10-19 11:23:23 -05:00 |
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linux-wave.do
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update wave-do
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2021-10-07 19:16:52 -04:00 |
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regression-wally.py
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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sim-buildroot
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-buildroot-batch
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-fp64
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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sim-fp64-batch
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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sim-wally
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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sim-wally-batch
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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wally-buildroot-batch.do
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Moved the test bench modules to a common directory.
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2021-07-30 14:16:14 -05:00 |
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wally-buildroot.do
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restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair
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2021-09-04 19:45:04 -04:00 |
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wally-fp64-batch.do
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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wally-fp64.do
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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wally-pipelined-batch.do
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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wally-pipelined-fpga.do
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Partially working sd card reader.
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2021-10-11 10:23:45 -05:00 |
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wally-pipelined.do
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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wave-all.do
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Fixed busybear by restoring InstrValidW needed by testbench
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2021-07-13 14:17:36 -04:00 |
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wave.do
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
