bbracker
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a02694a529
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-20 15:04:13 -04:00 |
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bbracker
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a3823ce3a9
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commented out old hack that used hardcoded addresses
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2021-07-20 15:03:55 -04:00 |
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David Harris
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e5e3f5abe6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-20 14:46:58 -04:00 |
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David Harris
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1f3dfa20f6
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flag for optional boottim
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2021-07-20 14:46:37 -04:00 |
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Ross Thompson
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4c785845f3
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-20 13:27:58 -05:00 |
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Ross Thompson
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00081ebc68
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Replaced FinalReadDataM with ReadDataM in dcache.
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2021-07-20 13:27:29 -05:00 |
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bbracker
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6b72b1f859
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ignore mhpmcounters because QEMU doesn't implement them
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2021-07-20 13:37:52 -04:00 |
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bbracker
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a1ea654b11
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-20 12:08:46 -04:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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bbracker
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077662bfa1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-20 05:40:49 -04:00 |
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bbracker
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9e658466e6
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testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
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2021-07-20 05:40:39 -04:00 |
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James E. Stine
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12e09a7ace
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slight mod to fpdiv - still bug in batch vs. non-batch
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2021-07-20 01:47:46 -04:00 |
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bbracker
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3b10ea9785
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major fixes to CSR checking
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2021-07-20 00:22:07 -04:00 |
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Ross Thompson
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365485bd8b
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Added performance counters for dcache access and dcache miss.
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2021-07-19 22:12:20 -05:00 |
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Ross Thompson
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508c3e35af
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Restored TIM range.
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2021-07-19 21:17:31 -05:00 |
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bbracker
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99fa2bbbc3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 19:30:40 -04:00 |
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bbracker
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cb15d7e4c7
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change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)
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2021-07-19 19:30:29 -04:00 |
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David Harris
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23b76a724d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 18:19:59 -04:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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bbracker
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c1d63fe77c
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MemRWM shouldn't factor into PCD checking
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2021-07-19 18:03:30 -04:00 |
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bbracker
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4d10cfc98b
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create qemu_output.txt
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2021-07-19 18:02:41 -04:00 |
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bbracker
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c8203c171e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 17:11:49 -04:00 |
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bbracker
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f7d040af1e
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make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
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2021-07-19 17:11:42 -04:00 |
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Kip Macsai-Goren
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5880cbafe4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 16:46:46 -04:00 |
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bbracker
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1aeef4e7d1
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remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
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2021-07-19 16:22:05 -04:00 |
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bbracker
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bc5222e721
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put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
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2021-07-19 16:19:24 -04:00 |
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bbracker
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65df5c087b
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adapt testbench to removal of ReadDataWEn signal
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2021-07-19 15:42:14 -04:00 |
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bbracker
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ae5663a244
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adapt testbench to removal of signal
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2021-07-19 15:41:50 -04:00 |
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bbracker
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64e0fe4c5a
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whoops MTIMECMP is always 64 bits
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2021-07-19 15:40:53 -04:00 |
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bbracker
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bdb1ece183
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 15:13:14 -04:00 |
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bbracker
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cd469035be
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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Kip Macsai-Goren
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2614df627e
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added changes to priority encoders from synthesis branch (correctly this time I hope)
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2021-07-19 15:06:14 -04:00 |
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Ross Thompson
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bf3ca50a9a
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Furture simplification of the dcache ReadDataW update.
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2021-07-19 12:46:31 -05:00 |
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Ross Thompson
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9f76e1d64d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-19 12:32:35 -05:00 |
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Ross Thompson
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b61dad4b83
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Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
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2021-07-19 12:32:16 -05:00 |
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bbracker
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1b0b9d0f79
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 13:21:04 -04:00 |
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bbracker
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f31a0ded75
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change buildroot expectations to match reality
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2021-07-19 13:20:53 -04:00 |
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bbracker
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67eb1f5c6b
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change sram1rw to have a small delay so that we don't have signals changing on clock edges
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2021-07-19 11:30:07 -04:00 |
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David Harris
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2ed6285a3d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 10:34:18 -04:00 |
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James Stine
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7d571f27a6
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delete sbtm_a4 and sbtm_a5 as they are not needed
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2021-07-19 08:06:00 -05:00 |
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James Stine
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186b5dee69
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remove sbtm3.sv - not needed
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2021-07-19 08:00:53 -05:00 |
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James Stine
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5b1f9797f5
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update part I on sbtm change
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2021-07-19 07:59:27 -05:00 |
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David Harris
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8e01007d1c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 00:25:06 -04:00 |
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Katherine Parry
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c9180f4ebd
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FDIV and FSQRT passes when simulating in modelsim
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2021-07-18 23:00:04 -04:00 |
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bbracker
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e4a50a5bb8
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change memread testvectors to not left-shift bytes and half-words
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2021-07-18 21:49:53 -04:00 |
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David Harris
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46ab609498
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Updated FMA1 with parameterized size
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2021-07-18 20:40:49 -04:00 |
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bbracker
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5e9dcb3f1c
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linux testbench progress
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2021-07-18 18:47:40 -04:00 |
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David Harris
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ed64d37e65
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-18 17:36:29 -04:00 |
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David Harris
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4f8f52f283
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Added FLEN, NE, NF to config and started using these in FMA1
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2021-07-18 17:28:25 -04:00 |
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Katherine Parry
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60dabb9094
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fdivsqrt inegrated, but not completley working
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2021-07-18 14:03:37 -04:00 |
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