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change sram1rw to have a small delay so that we don't have signals changing on clock edges

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bbracker 2021-07-19 11:30:07 -04:00
parent 7d571f27a6
commit 67eb1f5c6b
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/cache/sram1rw.sv vendored
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@ -15,7 +15,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
always_ff @(posedge clk) begin
ReadData <= StoredData[Addr];
if (WriteEnable) begin
StoredData[Addr] <= WriteData;
StoredData[Addr] <= #1 WriteData;
end
end
endmodule