bbracker 077662bfa1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-07-20 05:40:49 -04:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Restored TIM range.	2021-07-19 21:17:31 -05:00
linux-testgen	change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)	2021-07-19 19:30:29 -04:00
misc
ppa
regression	remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux	2021-07-19 16:22:05 -04:00
src	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
testbench	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
testgen
lint-wally