Ross Thompson
1f0821da0d
IFU and LSU now share the same busdp module.
2022-01-31 16:25:41 -06:00
Ross Thompson
86bac2a083
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
e4ee630a3e
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
a4f6653cd8
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Ross Thompson
ac50a36aac
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
David Harris
30cc27e719
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
Ross Thompson
db0a0bd29e
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
cc5a9a015b
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937
IFU simplifications.
2022-01-26 13:54:59 -06:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
cf50beb958
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
8ef70389d3
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
03010845f5
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
73ad5715f4
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
b8f4eb2997
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
2e8f5e06bd
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
Ross Thompson
77efcad15b
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
David Harris
32590d484c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
