Ross Thompson
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99e0e5c817
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Possible fix.
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2022-08-28 13:10:47 -05:00 |
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David Harris
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35d0a951d2
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Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
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2022-08-27 20:31:09 -07:00 |
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David Harris
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921a49921b
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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af2e71046e
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Fixed rv32e LSU and IFU issues
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2022-08-25 20:02:38 -07:00 |
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Ross Thompson
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e70c90d351
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Finally resolved the issues with the rv32ic and rv64ic configurations.
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2022-08-25 16:00:55 -05:00 |
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Ross Thompson
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ad3e632119
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Almost fixed issues with irom and dtim address selection.
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2022-08-25 15:52:25 -05:00 |
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Ross Thompson
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32f86b1b6b
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Still not working with rv32ic.
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2022-08-25 15:03:54 -05:00 |
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Ross Thompson
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502eb0f5d1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 14:40:52 -05:00 |
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David Harris
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d7be94fab2
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Cleaned up SelBusWord
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2022-08-25 11:18:13 -07:00 |
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David Harris
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7a129af9ad
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Removed M sufix from busdp signals
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2022-08-25 11:13:01 -07:00 |
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David Harris
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84ba62a04c
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Renamed LSUFunct3M to Funct3 in busdp
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2022-08-25 11:08:12 -07:00 |
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David Harris
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78618f5fc0
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Renaming LSU signals from busdp
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2022-08-25 11:05:10 -07:00 |
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David Harris
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cd02c894df
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renamed BusBuffer to FetchBuffer
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2022-08-25 10:44:39 -07:00 |
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David Harris
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5dc4fb757a
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Continued busdp/ebu simplification
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2022-08-25 10:20:02 -07:00 |
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David Harris
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89860588b8
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Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
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2022-08-25 09:52:08 -07:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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David Harris
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4ecdbb308a
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Renamed DCache to Cache in busdp/busfsm signal interface
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2022-08-25 06:21:22 -07:00 |
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David Harris
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a3828420c0
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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2022-08-25 04:06:27 -07:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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Ross Thompson
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cd0da2e3b3
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
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2022-08-19 18:07:44 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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f7e64fcd69
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Fixed fstore2 in cache?
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2022-08-01 22:04:44 -05:00 |
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Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Madeleine Masser-Frye
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cb33d2289b
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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Katherine Parry
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6baded9121
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added rv32 double precision stores - untested
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2022-06-28 21:33:31 +00:00 |
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slmnemo
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054cf5f7b0
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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slmnemo
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284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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slmnemo
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73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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c7ec9282fe
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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847c7930c4
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added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
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08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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slmnemo
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8c8a7daec2
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Fixed grammar on two comments in bpred.sv
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2022-05-16 22:41:18 +00:00 |
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David Harris
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ce24c080d5
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More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
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David Harris
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5670f77de2
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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David Harris
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eaa0d44980
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Fixed WFI decoding in IFU
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2022-04-18 19:02:08 +00:00 |
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Shreya Sanghai
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6f0085201b
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replaced k with bpred size
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2022-04-18 04:21:03 +00:00 |
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David Harris
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0932d4df46
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Added WFI support to IFU to keep it in the pipeline
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2022-04-14 17:26:17 +00:00 |
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Ross Thompson
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396f697d2f
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Hacky fix to prevent ITLBMissF and TrapM bug.
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2022-04-12 17:56:23 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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