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183 Commits

Author SHA1 Message Date
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Shreya Sanghai
df149d1be7 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
ShreyaSanghai
28a9c6ba56 added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
b544526766 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
Jarred Allen
39bf2347bc Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Jarred Allen
0290568a52 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
ba95557c44 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
Ross Thompson
1c6e37120e Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
84ad1353e4 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Ross Thompson
4fb7a1e0a6 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
0f8fe8fb3b Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
827993598d Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Jarred Allen
6ce52f9b80 Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
f9cf05a7d4 Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
c5f99c4a34 Revert "Change flop to listen to StallF" 
This reverts commit c8028710a5.
 2021-03-20 17:34:19 -04:00
Jarred Allen
c8028710a5 Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Jarred Allen
a82aa23399 Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
ac9fd5a323 Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb Get non-jump case working 2021-03-14 14:46:21 -04:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039 More progress 2021-03-09 21:16:07 -05:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Jarred Allen
41f682f848 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Ross Thompson
9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
Ross Thompson
78db3654c6 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Ross Thompson
3ec1f668fc added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00