Brett Mathis
162f2df880
FPU Pipeline completed - can begin integration
2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
David Harris
eb9787609e
testgen-PIPELINE python startup
2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615
adding PIPELINE tests
2021-03-25 13:07:25 -04:00
Teo Ene
51291949d8
Config file for ppa experiments
2021-03-25 10:23:21 -05:00
David Harris
a8abd47fbc
Added PPA README
2021-03-25 11:21:31 -04:00
Thomas Fleming
e3900bd0fa
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-25 02:35:21 -04:00
bbracker
a3788eb218
added 1 tick delay to dtim flops
2021-03-25 02:23:30 -04:00
bbracker
02e924e55a
instrfaults not respecting stalls bugfix
2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d
upgraded gpio bus interface
2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc
future work comment about suspicious-looking verilog in csri.sv
2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822
Add all PMP addr registers
2021-03-24 21:58:33 -04:00
Teo Ene
a3aa103dc7
Fix typo from last commit
2021-03-24 17:09:58 -05:00
Teo Ene
4427b5ec01
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-24 17:04:48 -05:00
Teo Ene
e43849b82c
Updated coremark_bare testbench for IM
2021-03-24 17:04:43 -05:00
Katherine Parry
18cb1f4873
fixed various bugs in the FMA
2021-03-24 21:51:17 +00:00
Teo Ene
385ce9a8f9
Added BPTYPE to coremark_bare config
2021-03-24 16:38:29 -05:00
Domenico Ottolia
d67e28bf50
re-organize privileged tests to be in rv64p to rv32p folders
2021-03-24 13:51:25 -04:00
Katherine Parry
56dc8de009
fixed various bugs in the FMA
2021-03-24 01:35:32 +00:00
Teo Ene
ef3d2dda48
Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
2021-03-23 15:21:13 -05:00
Shreya Sanghai
1d6a2989ed
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Jarred Allen
7da8af4c68
Another tweak to regression-wally.py comments
2021-03-23 00:18:38 -04:00
Jarred Allen
82de84469f
Slight change to regression-wally.py comments
2021-03-23 00:02:40 -04:00
Noah Boorstin
849641f31e
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
bbracker
5efd5958e7
added delays to uart AHB signals
2021-03-22 15:40:29 -04:00
Noah Boorstin
2aa76b27e1
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Noah Boorstin
74bcd9b994
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
bbracker
11d4a8ab34
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702
fixed various bugs in the FMA
2021-03-21 22:53:04 +00:00
Katherine Parry
e317e7511e
messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic
2021-03-20 02:05:16 +00:00
bbracker
85363e941d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
Shreya Sanghai
09faa40eb6
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c
Fixed minor bug with the size of gshare.
2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Thomas Fleming
7d4906b1c7
Improve page table creation in python file
2021-03-18 14:27:09 -04:00
Noah Boorstin
bc1a0c6ee7
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e
everyone gets a bootram
2021-03-18 12:35:37 -04:00
Noah Boorstin
ced2a32d21
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Teo Ene
57f1ca5259
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Teo Ene
4fd0ecff69
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
7446a7b479
fix to last commit
2021-03-17 15:07:02 -05:00
Teo Ene
3e849f99a6
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
d72d774a0b
addition to last commit
2021-03-17 14:52:31 -05:00
Teo Ene
dfe6df2e00
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008
fixing coremark branch prediction
2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
d0ddb5f461
replicating coremark changes into coremark bare
2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
da758e9e14
Merge branch '3_3_2021' into main
...
Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Ross Thompson
f070aae847
Fixed issue with sim-wally-batch. Are people still using this script?
2021-03-17 11:17:52 -05:00
Ross Thompson
3618a39087
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Domenico Ottolia
487b198055
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-16 23:27:09 -04:00
Domenico Ottolia
748372dc45
Add test runner for privileged
2021-03-16 23:26:59 -04:00
Noah Boorstin
bfa7aedd35
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Noah Boorstin
e7fae21eb8
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Domenico Ottolia
d354cbd37d
Add privileged testbench
2021-03-16 20:28:38 -04:00
Domenico Ottolia
82ea97e304
Add privileged tests for mcause
2021-03-16 19:22:36 -04:00
Domenico Ottolia
1ceb7a7431
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-16 19:12:21 -04:00
Jarred Allen
152ffd16e2
Undo accidental change
2021-03-16 18:16:00 -04:00
Jarred Allen
ae5417195a
Condense the parallel and non-parallel wally-pipelined-batch.do files into one
2021-03-16 18:15:13 -04:00
Jarred Allen
f6cbe44cbd
Change busybear to only check that first 100k instructions load
2021-03-16 17:43:39 -04:00
Shreya Sanghai
36f0631203
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Domenico Ottolia
b2faf3c888
Add privileged tests folder
2021-03-16 16:11:20 -04:00
Shreya Sanghai
9eed875886
added global history branch predictor
2021-03-16 16:06:40 -04:00
Shreya Sanghai
08e9149e20
made performance counters count branch misprediction
2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a
Merge branch 'counters' into main
...
added a configurable number of performance counters
2021-03-16 11:01:30 -04:00
Noah Boorstin
9e1612c166
remove regression-wally.sh
2021-03-15 19:03:57 -04:00
Noah Boorstin
400791163e
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
f2a6e8c6cf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
2021-03-15 12:06:18 -05:00
Ross Thompson
806cfc4ea5
Fixed the parallel script so the rv64ic passes.
...
rv32ic and busybear still have issues.
2021-03-15 12:04:59 -05:00
bbracker
345254b5a3
slightly smarter dtim HREADY
2021-03-13 06:55:34 -05:00
bbracker
c5015e5809
imem rd2 adrbits bugfix
2021-03-13 00:10:41 -05:00
Ross Thompson
940d892f29
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 20:18:35 -06:00
Ross Thompson
7ceef2b0c6
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
bbracker
f4fb546969
clint HREADY signal update
2021-03-12 20:23:55 -05:00
Ross Thompson
86078d856f
Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix.
2021-03-12 15:29:02 -06:00
Ross Thompson
6ee97830f7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
David Harris
56b690ccb9
Drafted rv32a tests
2021-03-12 00:06:23 -05:00
David Harris
865c103599
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
cc94046084
test regression script: add commented out rv32ic tests
2021-03-11 12:57:54 -05:00
Noah Boorstin
394b79b5de
add rv32ic regression test
2021-03-11 12:40:29 -05:00
Noah Boorstin
54fa16d783
test regression script: parallalize better
2021-03-11 12:25:20 -05:00
Noah Boorstin
aba54659bf
test regression script: try adding verilator checking also
2021-03-11 07:32:31 +00:00
Noah Boorstin
81c14f899d
try adding delays to test regression script
2021-03-11 06:59:50 +00:00
Noah Boorstin
1093b07670
this is just a test for now, try to reimplement regression-wally in bash
2021-03-11 06:45:45 +00:00
Noah Boorstin
a8b242a6ef
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
42275e92ed
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
Ross Thompson
845115302e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Noah Boorstin
2c25e270a2
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
Ross Thompson
50a92247b3
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
c2f340681d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1b206d5a3c
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
David Harris
9c7da510fb
Created atomic test vector and directories
2021-03-08 09:38:55 -05:00
Ross Thompson
d5f151eb0f
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
2b891196d9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 16:20:53 -05:00
Noah Boorstin
3c5be59e9b
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Thomas Fleming
be6ee84d87
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Noah Boorstin
86142e764a
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
889d2c0b85
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
850a2e9329
added a delay to sel signals
2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7
more merging fixes
2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0
remove deprecated mem signals
2021-03-05 14:27:38 -05:00
bbracker
19fc7d2381
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
0f4a231543
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
1a11b60664
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Thomas Fleming
2e2eb5839f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
5a3ba1174e
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Ross Thompson
a662aa487c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 17:31:27 -06:00
Ross Thompson
264480f258
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7
fixed various bugs
2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77
fixed various bugs
2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad
fixed various bugs
2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996
fixed various bugs
2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0
fixed various bugs
2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8
fixed various bugs
2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46
fixed various bugs
2021-03-04 22:18:19 +00:00
Thomas Fleming
3303a013ef
Merge branch 'walker' into main
2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea
busybear: comment out instraccessfaultf for imem for now
2021-03-04 20:26:41 +00:00
Noah Boorstin
827dfd774b
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Shreya Sanghai
246dbd05e7
fixed bugs
2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117
added performance counters
2021-03-04 11:42:52 -05:00
bbracker
448cba2a5b
JALR testing
2021-03-04 10:37:30 -05:00
Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
