Ross Thompson
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e774dd2db9
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Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
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2022-12-15 09:53:35 -06:00 |
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Ross Thompson
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b02550b05c
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Merge branch 'main' into hazards
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2022-12-15 08:44:59 -06:00 |
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David Harris
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33aca5d35e
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Added IDIV_ON_FPU flag to control whether integer division uses FPU
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2022-12-15 06:37:55 -08:00 |
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David Harris
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5f637ef4a7
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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cturek
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8829e627eb
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Fixed BZero and initU/initUM muxes
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2022-12-14 16:44:46 +00:00 |
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Ross Thompson
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09dcb56217
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Signal renames to reflect figures.
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2022-12-14 09:49:15 -06:00 |
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Ross Thompson
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a3ec829b80
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-14 09:34:34 -06:00 |
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Ross Thompson
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6da7849d27
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Reduced complexity of linebytemask.
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2022-12-14 09:34:29 -06:00 |
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cturek
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ed59736a4b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-14 15:13:44 +00:00 |
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Ross Thompson
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1ba1bed0b0
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Broken dont' use.
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2022-12-11 23:24:01 -06:00 |
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Ross Thompson
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0716aedbd5
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Removed unused flushf.
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2022-12-11 16:28:11 -06:00 |
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Ross Thompson
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115e9e7bb3
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Renamed CPUBusy to GatedStallF in IFU.
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2022-12-11 15:54:19 -06:00 |
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Ross Thompson
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ffc5bce0b6
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Renamed CPUBusy in LSU.
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2022-12-11 15:52:51 -06:00 |
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Ross Thompson
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c50a2bd8bf
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Changed CPUBusy to Stall in ebu modules.
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2022-12-11 15:51:35 -06:00 |
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Ross Thompson
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3ddf509f28
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Renamed CPUBusy to Stall in cache.
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2022-12-11 15:49:34 -06:00 |
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Ross Thompson
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4aadd87679
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Moved CPUBusy out of HPTW.
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2022-12-11 15:48:00 -06:00 |
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cturek
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f57211bb49
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Ross Thompson
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d15cf5c65c
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Added comments about why it is not possible to use FlushWay and VictimWay directly.
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2022-12-09 17:07:35 -06:00 |
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Ross Thompson
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1463e9b1d4
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Finished merge of kip and ross's ifu fix.
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2022-12-09 16:52:22 -06:00 |
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Ross Thompson
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6f01ea12e8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-09 16:42:16 -06:00 |
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Ross Thompson
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38adcb5b17
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Minor simplification of cacheway way selection muxes.
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2022-12-09 16:42:05 -06:00 |
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Kip Macsai-Goren
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f486a763d9
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Ross Thompson
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033f844d09
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-06 10:38:14 -06:00 |
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Ross Thompson
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9ee2d84c7c
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Fixed bug Kip found.
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
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2022-12-06 10:37:45 -06:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6c0ef05db
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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1d268fded4
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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ae32e2a9ee
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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7411d50a78
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added all 32 bit tests to 64 bit periph tests except gpio
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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badc684f07
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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282d06b45f
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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9806babe9e
|
Renamed SelBusBuffer to SelFetchBuffer.
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2022-12-05 17:51:13 -06:00 |
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Ross Thompson
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0fdbfb87eb
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Removed commented code.
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2022-12-05 17:21:56 -06:00 |
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Ross Thompson
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85366a287b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-05 17:20:12 -06:00 |
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Ross Thompson
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bcb927d172
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Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
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2022-12-05 17:19:51 -06:00 |
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rachanaerra
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4f042b0adb
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updated constraints file
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2022-12-05 15:05:21 -06:00 |
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Ross Thompson
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2bcaacb179
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Cache signal renames.
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2022-12-04 16:09:09 -06:00 |
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Ross Thompson
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b84b709182
|
Optimized way selection logic.
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2022-12-04 12:30:56 -06:00 |
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Ross Thompson
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74d5ccc2b1
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Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
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2022-12-04 01:20:51 -06:00 |
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Ross Thompson
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62e495c739
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Moved selectedway mux into cacheway. It makes way more sense there.
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2022-12-04 01:15:47 -06:00 |
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Ross Thompson
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e1ac736d43
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Rename LineByteMux to FetchbufferbyteSel.
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2022-12-04 01:00:04 -06:00 |
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Ross Thompson
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128b3d20e7
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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de99663b97
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Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
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2022-12-04 00:01:58 +00:00 |
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Ross Thompson
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b7d004b261
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Removed old flow directory.
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2022-12-03 10:28:39 -06:00 |
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Ross Thompson
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ec8ae6e3a8
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removed imperas-riscv-tests-deleteme
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2022-12-03 00:18:42 +00:00 |
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Ross Thompson
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d969ae35e5
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removed unusedsrc directory as it was large 384MB!
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2022-12-02 17:37:06 -06:00 |
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Ross Thompson
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9d960dec65
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Removed design ware mult.
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2022-12-02 16:51:12 -06:00 |
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cturek
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70b89e5214
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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cturek
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1f32603c30
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Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
|
9395414df3
|
Renamed FPUStallD to FCvtIntStallD
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2022-12-02 11:55:23 -08:00 |
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