Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
baa2b5d15f
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
Ross Thompson
47e16f5629
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
Ross Thompson
224e3b2991
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
Ross Thompson
49f6eec579
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
1cc258ade1
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Ross Thompson
f26d635614
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29
Write Hits and Write Misses without eviction are working correctly! The next
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step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
Ross Thompson
b1ceeb40df
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
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I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
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Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Ross Thompson
94c3fde724
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31
completed read miss branch through dcache fsm.
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The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
Ross Thompson
910ddb83ae
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670
Partial implementation of the data cache. Missing the fsm.
2021-07-07 17:52:16 -05:00
Ross Thompson
412691df2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
Abe
8854532a79
Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
2021-07-06 12:37:58 -04:00
Ross Thompson
7af8cfba18
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 10:41:45 -05:00
Ross Thompson
6e7e318396
Fixed bug in the LSU pagetable walker interlock.
2021-07-06 10:41:36 -05:00
David Harris
30fdd7abc8
Cleaned up tlb output muxing
2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
2021-07-06 10:38:30 -04:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
David Harris
f805aea236
Implemented TSR, TW, TVM, MXR status bits
2021-07-06 01:32:05 -04:00
David Harris
8b23162d6d
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
71711c54c9
Don't generate HPTW when MEM_VIRTMEM=0
2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b
Fixed combo loop in the page table walker.
2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-05 16:07:27 -05:00
David Harris
5f91b339aa
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 10:30:46 -04:00
David Harris
ac163e091c
Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported
2021-07-04 19:33:46 -04:00
David Harris
004cac91e1
Simplified PLIC with generate
2021-07-04 19:17:15 -04:00
David Harris
0aae58abed
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 19:02:56 -04:00
David Harris
600e7802dd
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 18:56:30 -04:00
David Harris
db5a06beaf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:55:24 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
bbracker
287935c09d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:17:16 -04:00
David Harris
07f2064c19
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
bbracker
ceac0352f7
ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
2021-07-04 18:17:06 -04:00
Ross Thompson
b2c5c3f637
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 17:07:57 -05:00
David Harris
b0f199b574
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
Ross Thompson
02721c29dc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:54:31 -05:00
Ross Thompson
17f37f21ff
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:53:16 -05:00
