David Harris d58cad89a8 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines		2021-07-06 10:38:30 -04:00
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cache	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 18:55:24 -04:00
ebu	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
fpu	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
generic	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
hazard	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ieu	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
ifu	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00
lsu	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00
mmu	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
uncore	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
wally	Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb	2021-07-04 18:56:30 -04:00