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ceac0352f7
cvw/wally-pipelined/src
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bbracker ceac0352f7 ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
2021-07-04 18:17:06 -04:00
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cache ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF 2021-07-04 18:17:06 -04:00
ebu Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
fpu Commented out some unused modules 2021-07-04 01:40:27 -04:00
generic Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
hazard Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
ieu Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
ifu Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
lsu Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
mmu Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
muldiv Commented out some unused modules 2021-07-04 01:40:27 -04:00
privileged Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
uncore for GPIO give priority to clearing interrupts 2021-07-04 17:20:16 -04:00
wally Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00