Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,663 Commits 14 Branches 1 Tag 31 MiB
3b1fe78bdc
Commit Graph

347 Commits

Author SHA1 Message Date
David Harris
5956fbdd62 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
David Harris
921a49921b Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
6409548c8b Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
906f6f2990 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
Ross Thompson
109bcd470e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
David Harris
6222e15946 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
32f86b1b6b Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
Ross Thompson
4ad7ccc7f7 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
bd9401179d BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
David Harris
fe3147806d removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
b3a13a01f8 Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
Ross Thompson
b650d7e05a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
07b2858890 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
9e3d13ca52 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
7c91ed38a3 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
b795cf4731 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
dad6770fc3 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
David Harris
da275e3c26 Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
ae4ea00ff0 fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
094aacdf6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
ccf8ccfa24 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
539174f6f6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
Ross Thompson
70032bf8f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Katherine Parry
ee7932c804 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
2bbfd67082 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
44c30ec082 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
170601af0b Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
fbe3a1af12 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
261b9aa5a1 commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
0d98ff74b4 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
5d7171f6f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
526f70e772 commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
49565f944c Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
bd918d37ba added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
a17361870f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
6e9b4f4075 removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
270216dd02 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
67c99d3d1a added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Daniel Torres
d33d0d22bd commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Katherine Parry
4c2afbbc4f moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
e599f82b29 moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
5bb1478859 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
191c7a2ee3 added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
David Harris
d10ad0e883 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
DTowersM
5a68ff9afb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
d55833e4f3 new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
DTowersM
47a990d9f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
1e8ccf3449 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
dab87811e9 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
Daniel Torres
a384a6465b reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
50b9b4557c added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
slmnemo
448c9fdbb9 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
d058ec6329 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
Katherine Parry
5133b08161 generate qsel4 in verilog 2022-06-23 21:38:04 +00:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
David Harris
8537b883d1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:45:28 +00:00
slmnemo
2b2760f5bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
2b2ddbcc5e Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Daniel Torres
d077199608 embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1ef5ed8005 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
dcdd3702c3 removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
3a5c02b44a arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
David Harris
ecd733942a Removed testbench.sv.bak 2022-06-14 22:04:38 +00:00
DTowersM
919c1818a8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00