cturek
39bf6a456e
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
cturek
890b26466f
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
cturek
2a45787b37
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
03f68a4cf5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
36d9a00471
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
51fc4de0e1
small signal cleanup
2022-10-26 18:42:49 +00:00
cturek
544c142c4f
abs for int inputs
2022-10-26 16:18:05 +00:00
cturek
e401d12889
Added signed division to fdivsqrt
2022-10-26 16:13:41 +00:00
Jacob Pease
ec0cede2f2
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
cturek
94daa961b3
Started Integer Preprocessing
2022-10-25 17:48:43 +00:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
cc605a1966
Bit width error.
2022-10-24 13:48:47 -05:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
f9a04c13df
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
78586c5a7a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
611ea6882d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
1f207bcafb
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
e5cae3bfa0
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
5ad3ee6b54
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
de1e569ee9
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
61f7bad739
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
962ba5e4b8
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
a7ae593a68
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
2c80c2b35f
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
amaiuolo
a0712d1456
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4
added amaiuolo@hmc.edu
2022-10-13 22:36:52 +00:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
fccaad7f3f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
12a6a9f83b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
f711eb0bcf
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
b2f71b8255
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
Ross Thompson
a5c15fd801
Fixed first problem with the rv64i IROM.
2022-10-11 11:35:40 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
David Harris
a5a922d048
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
David Harris
6092ca757a
New fdivsqrtqsel4cmp module based on comparators rather than table lookup
2022-10-09 04:47:44 -07:00
David Harris
dceb6f9034
Moved shift into divsqrt stage and cleaned up comments
2022-10-09 04:45:45 -07:00
David Harris
55e4911cf0
fdivsqrt code cleanup
2022-10-09 03:37:27 -07:00
Ross Thompson
382ccf74a5
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
62951ec653
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
2144343c4a
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
2e578eb8d8
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
b52ab91028
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
a0c5833d6d
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
68aa1434b4
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
e6b36d0c02
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
3f59ea6b6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:38:49 -05:00
Ross Thompson
92d7be645b
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
