David Harris
183a2dcfb5
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
63c7c18771
Fixed lw by delaying read value by one cycle
2021-02-07 23:28:21 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
91f6858de7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12
Minor tweaks
2021-02-02 19:44:37 -05:00
Noah Boorstin
00d9e13d68
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
aee44bb343
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
c23afbda3a
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
Brett Mathis
94de3e9fb2
OSU FPU IP initial commit
2021-02-01 19:33:43 -06:00
David Harris
056b147b13
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217
Working on reading instruction from TIM
2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499
Adding stalls for memory delays
2021-01-30 01:43:49 -05:00
David Harris
9c81278f28
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
73a584b223
Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
2021-01-29 18:06:36 -05:00
David Harris
e700e404c9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
David Harris
dc2443c55b
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
David Harris
ed3cb83c10
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
David Harris
618c6e4813
Renamed modules in privileged unit
2021-01-28 23:21:12 -05:00
David Harris
05b755958f
Hint to optimize ifu
2021-01-28 21:40:48 -05:00
David Harris
fe0876027f
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
David Harris
ad5d4793b6
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
David Harris
f95d0690ca
Created DCU and moved memdp into DCU
2021-01-28 01:03:12 -05:00
David Harris
a50b6c2a15
Provided PC + 2 or 4 (PCLink) for JAL
2021-01-28 00:22:05 -05:00
David Harris
824014c5c0
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
David Harris
616afaba69
Moved privileged unit from datapath to hart
2021-01-27 07:46:52 -05:00
David Harris
b88508ca11
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
David Harris
1d9c741c00
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
David Harris
fa18052348
Added test configurations
2021-01-25 11:28:43 -05:00
Noah Boorstin
aea1c0cd2e
small busybear testbench changes
2021-01-24 20:43:47 -05:00
Noah Boorstin
e7288716f7
Linux testbench works now
...
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
2021-01-24 17:10:00 -05:00
Noah Boorstin
12a8f83025
Merge branch 'busybear' into main
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Merging busybear testbench into main, keeping main edits of wally src
2021-01-24 16:28:36 -05:00
Noah Boorstin
b08b86f561
sucessfully simulate first 30 instructions
...
still need to find a better solution to InstrAccessFault/DataAccessFault though
2021-01-23 19:01:44 -05:00
Noah Boorstin
a75d7e4555
More linux testbench fixes
...
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(
This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.
Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
2021-01-23 17:52:05 -05:00
Noah Boorstin
be62987dec
Linux test now gets through first 8 instructions!
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fixes the python parser:
get the value, not function name, of PC
only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
2021-01-23 16:46:45 -05:00
David Harris
3905e77e54
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 10:48:12 -05:00
David Harris
170c88bc06
Cleaned up regfile x0 tied to gnd
2021-01-23 10:22:20 -05:00
David Harris
93f8c6f29e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-23 10:19:28 -05:00
David Harris
6b9c6223be
Initial checkin of UART
2021-01-23 10:19:09 -05:00
Noah Boorstin
18f6aa716e
slightly more info on errors, add instruction decoding
2021-01-22 21:14:45 -05:00
Noah Boorstin
3b16766fde
change how testbench reads data
...
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
2021-01-22 20:27:01 -05:00
