324 Commits

Author	SHA1	Message	Date
bbracker	1aeef4e7d1	remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux	2021-07-19 16:22:05 -04:00
bbracker	cd469035be	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
Ross Thompson	9f76e1d64d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-19 12:32:35 -05:00
Ross Thompson	b61dad4b83	Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.	2021-07-19 12:32:16 -05:00
bbracker	f31a0ded75	change buildroot expectations to match reality	2021-07-19 13:20:53 -04:00
bbracker	e4a50a5bb8	change memread testvectors to not left-shift bytes and half-words	2021-07-18 21:49:53 -04:00
bbracker	5e9dcb3f1c	linux testbench progress	2021-07-18 18:47:40 -04:00
Katherine Parry	60dabb9094	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
bbracker	18fb282a37	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-17 14:46:38 -04:00
bbracker	4a3503281f	swapped out linux testbench signal names	2021-07-17 14:46:18 -04:00
David Harris	87aa527de7	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
Ross Thompson	6521d2b468	Also changed the shadow ram's dcache copy widths. ... Merge branch 'dcache' into main	2021-07-16 14:21:09 -05:00
Ross Thompson	b3bf04d474	Updated wave file.	2021-07-16 12:34:37 -05:00
Ross Thompson	46bce70e42	Fixed walker fault interaction with dcache.	2021-07-16 12:22:13 -05:00
bbracker	01ca22af49	changed stop of linux boot from arch_cpu_idle to do_idle	2021-07-16 12:27:15 -04:00
Ross Thompson	e5d624c1fa	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
Ross Thompson	fa26aec588	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
Ross Thompson	fd1de6b047	Updated wave file.	2021-07-15 11:04:49 -05:00
Ross Thompson	704f4f724e	dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.	2021-07-14 23:08:07 -05:00
Ross Thompson	ba1e1ec231	Finally have the ptw correctly walking through the dcache to update the itlb. ... Still not working fully.	2021-07-14 22:26:07 -05:00
Katherine Parry	c74d26eea4	Fixed lint warning	2021-07-14 21:24:48 -04:00
Ross Thompson	2c946a282f	Fixed d cache not honoring StallW for uncache writes and reads.	2021-07-14 17:23:28 -05:00
Ross Thompson	e91501985c	Routed CommittedM and PendingInterruptM through the lsu arb.	2021-07-14 16:18:09 -05:00
Ross Thompson	9b756d6a94	Implemented uncached reads.	2021-07-13 23:03:09 -05:00
Ross Thompson	3e57c899a2	Partially working changes to support uncached memory access. Not sure what CommitedM is.	2021-07-13 17:24:59 -05:00
Ross Thompson	baa2b5d15f	Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.	2021-07-13 14:51:42 -05:00
Ross Thompson	3c1a717399	Fixed the fetch buffer accidental overwrite on eviction.	2021-07-13 14:21:29 -05:00
Ross Thompson	32f27cfecf	Dcache AHB address generation was wrong. Needed to zero the offset.	2021-07-13 14:19:04 -05:00
Ross Thompson	afc1bc9c38	Moved StoreStall into the hazard unit instead of in the d cache.	2021-07-13 13:20:50 -05:00
David Harris	9de97c1e20	Fixed busybear by restoring InstrValidW needed by testbench	2021-07-13 14:17:36 -04:00
Katherine Parry	efdec72df1	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
Ross Thompson	e594eb540d	Got the shadow ram cache flush working.	2021-07-13 10:03:47 -05:00
Ross Thompson	49f6eec579	Team work on solving the dcache data inconsistency problem.	2021-07-12 23:46:32 -05:00
Ross Thompson	1cc258ade1	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
Katherine Parry	36f59f3c99	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
Ross Thompson	60ed023734	Actually writes the correct data now on stores.	2021-07-10 17:48:47 -05:00
Ross Thompson	6e7e318396	Fixed bug in the LSU pagetable walker interlock.	2021-07-06 10:41:36 -05:00
Ross Thompson	2a62ee2e70	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-05 16:07:27 -05:00
David Harris	5f91b339aa	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
Ross Thompson	a252416535	Removed the TranslationVAdrQ as it is not necessary.	2021-07-04 16:49:34 -05:00
Ross Thompson	7f62808544	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-04 16:19:39 -05:00
Ross Thompson	5b70eb86b0	relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.	2021-07-04 13:49:38 -05:00
David Harris	9645b023c9	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
Ben Bracker	59b177beac	stop busybear from hanging	2021-07-02 17:22:09 -05:00
Ross Thompson	dbd33465e1	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
Ross Thompson	61027f650c	OMG. It's working!	2021-07-01 17:37:53 -05:00
Ross Thompson	2dc349ea6f	Fixed the wrong virtual address write into the dtlb.	2021-07-01 16:55:16 -05:00
Ross Thompson	88a18496cf	Got some stores working in virtual memory.	2021-07-01 12:49:09 -05:00
Ross Thompson	002c32d2ad	The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.	2021-06-30 17:02:36 -05:00
Ross Thompson	9ec624702d	Major rewrite of ptw to remove combo loop.	2021-06-30 16:25:03 -05:00