Ross Thompson
0670c57fd2
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
Ross Thompson
fe22fd2db8
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
7f1653f073
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
997c13a521
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
fac2431add
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
89ad4477e4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
857f59ab5c
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
ddbdd0d5a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
f6c88666cf
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
0fe63282f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
46a232b862
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
9954d16fc9
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
12c34c25f3
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
690815ca51
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
8a035104ac
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
778ba6bbf5
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
1459d840ed
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
309e6c3dc1
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
bb99480fca
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
77260643eb
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
e7190b0690
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Ross Thompson
fec40a1b75
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
James E. Stine
bb5404e14a
Update FPregfile to use more compact code and better structure for ease in reading
2021-05-25 13:21:59 -05:00
Ross Thompson
063e458ff0
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
16e037b8e9
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
James E. Stine
c4f3f2f783
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
295263e122
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
Ross Thompson
c5310e85c1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-24 14:28:41 -05:00
Katherine Parry
90d5fdba04
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Ross Thompson
65632cb7c9
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
72f77656a3
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
James E. Stine
6f38b7633c
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
70968a4ec3
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
bf6337f2f7
plic implementation optimizations
2021-05-19 18:10:48 +00:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
James E. Stine
e808b06b82
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
5506efc115
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
865b3ee219
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
b9e099d53c
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
ea4e76938e
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
1ec6ad14f6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
8a7fc959eb
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
19ac77d3fa
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Ross Thompson
21acc45121
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
52e4c49bbb
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
3a3c88f5b1
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
c9e5af30fa
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
