Ross Thompson 21acc45121 Fixed synthesis bug with icache valid bit.		2021-05-04 13:03:08 -05:00
..
cache	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
dmem	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
ebu	Remove remnants of InstrReadC	2021-05-03 17:36:25 -04:00
fpu	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
ieu	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
ifu	Fixed synthesis bug with icache valid bit.	2021-05-04 13:03:08 -05:00
mmu	Refactor tlb_ram to use flop primitives	2021-04-22 01:52:43 -04:00
muldiv	Fixed lint error in div	2021-05-03 09:26:12 -04:00
privileged	Fix bug in PMP checker	2021-05-04 03:14:07 -04:00
uncore	Rolled back fflush on uart. Use -syncio in Modelsim command line instead.	2021-05-03 20:04:44 -04:00
wally	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 14:02:19 -04:00