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10,532 Commits 4 Branches 2 Tags 53 MiB
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144 Commits

Author SHA1 Message Date
Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params 2024-11-16 12:35:37 -08:00
Rose Thompson
e22f30ec14 Better name for CacheSetTag2. 2024-11-13 12:24:35 -06:00
Rose Thompson
383fce5522 Fixed the issue with cbo.clean. 2024-11-12 14:38:44 -06:00
Rose Thompson
b7b7c79726 CBO.FLUSH was not clearing the valid bit if the cacheline was clean. 2024-11-12 14:16:55 -06:00
Rose Thompson
8a4868ac57 Resolved a bug in the cache but there are still mismatches with the cache simulator. 2024-11-12 11:35:29 -06:00
Rose Thompson
3137fd7db2 Resolved some of the issues with the cache simulator mismatching with Wally. The LRU was incorrectly updating it's state while the cache was stalled causin g the LRU state to be update when it should not be. 2024-11-11 14:23:58 -06:00
Rose Thompson
8fb1673ab3 Updated email address authorship for my files. 2024-10-15 10:27:53 -05:00
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
David Harris
2fc9edff45 Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly 2024-06-18 04:40:38 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Rose Thompson
84946919a4 Changed name CacheWriteData to WriteData. 2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99 Changed name of cache parameter NUMLINES to NUMSETS to better match book. 2024-05-28 17:55:43 -05:00
Rose Thompson
6c0b860742 Fixed the cache miss counter. 2024-04-24 16:14:51 -05:00
David Harris
6415bfc3c2 Code and testbench cleanup 2024-04-23 10:17:44 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
Rose Thompson
5b4d3f49b0 Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv. 2024-03-26 12:26:03 -05:00
Kunlin Han
22b59138f0 Remove all #delay from non-testbench. 2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912 Remove all #delay from non-testbench. 2024-03-13 10:31:40 -07:00
David Harris
c7c12cc3a8 Fixed Lint issue on cacheLRU 2024-03-06 14:00:57 -08:00
Rose Thompson
0d8c251fa4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-03-06 15:35:34 -06:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
Rose Thompson
c093f53c9c Merge branch 'main' of https://github.com/openhwgroup/cvw 
Cleaned up the cacheLRU.
 2024-03-05 11:08:40 -06:00
Rose Thompson
e8e0538f6c
Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush. 2024-03-05 10:33:47 -06:00
Rose Thompson
457d3481e7 How did this error get past for so long. 2024-03-04 17:58:41 -06:00
Rose Thompson
0222e8f42a Don't want to clear the lru bits on invalidation (clearvalid). 2024-03-04 17:52:41 -06:00
Rose Thompson
4c3d927474 Renamed CacheHit to Hit. 2024-03-01 11:00:24 -06:00
Rose Thompson
e72880fd89 Changed cachefsm state STATE_HIT to STATE_ACCESS. 2024-03-01 09:59:54 -06:00
Rose Thompson
85691f0e8b Simplified and clarified names in cacheLRU. 2024-02-29 17:18:01 -06:00
Rose Thompson
90ad5e7dab Updated the cache for book clarity. 2024-02-28 17:07:32 -06:00
David Harris
90e89ced1d Fixes for synthesis. HPTW change will break x detection 2024-02-26 04:20:08 -08:00
David Harris
6f53adad80 ifu cachefsm coverage 2024-02-08 13:15:06 -08:00
David Harris
66c1c71a56 Coverage improvements 2024-02-04 18:56:40 -08:00
David Harris
5d8d82414b Coverage improvements 2024-02-04 11:40:38 -08:00
David Harris
0abfe5cb55 Fixed some lint errors in derived configs 2024-01-31 11:39:59 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
David Harris
e8dde265be More coverage: CacheWay 2024-01-26 16:14:36 -08:00
David Harris
3620a10c0b Improved hptw and I CacheWays coverage 2024-01-26 14:55:51 -08:00
David Harris
4ffa5e7b0a Coverage improvements 2024-01-22 09:49:24 -08:00
Rose Thompson
2d3dc55986 Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting. 2024-01-17 12:19:10 -06:00
Rose Thompson
730efefc41 Cleanup. 2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
Rose Thompson
1d36ce3328 Fixed lint issue. 2023-12-18 12:03:54 -06:00
Rose Thompson
1ca9a8be6d I think I solved the AMO/store hazard issue introduced by removing the store delay hazard. 2023-12-14 16:31:02 -06:00
Rose Thompson
e089b421bb Got it working for the cache. 2023-12-13 20:24:46 -06:00
Rose Thompson
f592baa741 Closer. 2023-12-13 18:15:32 -06:00