Rose Thompson
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7ba891f607
|
Progress. I think the remaining bugs are in the regression test's signature.
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2023-11-01 17:51:48 -05:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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Rose Thompson
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5660eff57d
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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4984b3935f
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Progress
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2023-10-31 14:50:33 -05:00 |
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Rose Thompson
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5ca428d6a8
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Fixed bugs in misaligned test.
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2023-10-31 12:49:35 -05:00 |
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Rose Thompson
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c061440141
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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2241976d29
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Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
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2023-10-30 18:26:11 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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0fd5b3b2ce
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Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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5a4028064a
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Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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b4891d88db
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Added WALLY minfo test for rv32
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2023-10-15 06:48:22 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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f231c3d3a3
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correct delay0, fmt register test entries
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2023-10-12 15:13:23 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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12c3c98824
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Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
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2023-08-30 11:29:44 -05:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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cd3349bd26
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Added rv32 cboz test.
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2023-08-24 17:02:53 -05:00 |
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Ross Thompson
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914b6f9734
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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Ross Thompson
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7d51690b7c
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Oups forgot to include the 32-bit cbom test in previous commit.
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2023-08-24 09:04:41 -05:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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Ross Thompson
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d4c6ba627d
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Working CBO tests for 64 bit!
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2023-08-21 12:55:07 -05:00 |
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Ross Thompson
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5ed096e4bc
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Made a bunch of progress towards getting cbo instructions tested.
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2023-08-21 11:46:21 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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f68b9c224a
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Fixed WALLY-trap test case to use menvcfg
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2023-06-09 15:24:26 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
|
David Harris
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19096a812a
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Added Zifencei ISA to tests where necessary to support new compiler
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2023-05-16 11:18:27 -07:00 |
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David Harris
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0a7a159d69
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Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
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2023-05-14 06:58:29 -07:00 |
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Kip Macsai-Goren
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34200e8c76
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restored original virt mem tests when svadu is not supported
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2023-04-11 18:47:08 -07:00 |
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Kip Macsai-Goren
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c4766c8a02
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renamed virt mem tests to include svadu
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2023-04-11 18:46:37 -07:00 |
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Kip Macsai-Goren
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b2d6084eea
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removed unnecessary 'deadbeef's at the end of reference outputs
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2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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Kip Macsai-Goren
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e0b938b409
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Removed Trap outputs from writes covered by SVADU
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2023-04-11 17:41:57 -07:00 |
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Kip Macsai-Goren
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a899606c2b
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Removed Sail from virt mem tests due to sail not recognizing SVADU
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2023-04-11 17:41:31 -07:00 |
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Kip Macsai-Goren
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19305fe60a
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Added sail simulation to priv tests that support it
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2023-04-11 13:26:59 -07:00 |
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Kip Macsai-Goren
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a7c9d3d37b
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ported medelg fixes to 32 bit tests. Requires a make allclean
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2023-03-29 16:31:28 -07:00 |
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Kip Macsai-Goren
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2e151b6b08
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updated tests to reflect non-writeable bits of deleg
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2023-03-29 15:24:00 -07:00 |
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David Harris
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2e5c50e24a
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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David Harris
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e8904411ce
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Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
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2023-03-28 06:58:17 -07:00 |
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Kip Macsai-Goren
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106ed02a7e
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 7870148814.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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758da62a9f
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ported fixes to 32 bit tests
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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ff59fefcc9
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replaced inerrupt tests with allowed versions
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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6f15ae1225
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Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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7870148814
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added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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db6caedfec
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added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
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ab6b953a4b
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removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
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ac5c53a870
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Added correct causing and handling of S time interrupts to test suite.
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2023-03-04 15:04:17 -08:00 |
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David Harris
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f0c0111ab0
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Renamed section 12.3 to 8.3 in MMU test definitions
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2023-02-19 05:46:46 -08:00 |
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David Harris
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4883351bd2
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-28 18:18:53 -08:00 |
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Kip Macsai-Goren
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ee1bcf62ee
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Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
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2023-01-28 17:29:35 -08:00 |
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David Harris
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cea89f27cf
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Removed unused WALLY test references
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2023-01-27 07:25:04 -08:00 |
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David Harris
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2af94bf283
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Removed unused reference files
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2023-01-27 07:21:55 -08:00 |
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Kip Macsai-Goren
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964084f0b3
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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a37bde7452
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updated trap handler alignemnts to 64 bytes in priv tests
|
2022-12-22 14:23:04 -08:00 |
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David Harris
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ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
Ross Thompson
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f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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c41d58bd29
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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4c81b6fa5f
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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4ab99904a4
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added all 32 bit tests to 64 bit periph tests except gpio
|
2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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51e78d9e48
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
|
540d6c2f41
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added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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9b1765ce92
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
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Kip Macsai-Goren
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21e045eb7d
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added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
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Kip Macsai-Goren
|
90ef371abc
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
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Kip Macsai-Goren
|
c06da6e6fe
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
103514a8e0
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
21eca47d2e
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
6e45698b86
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Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
e603973dff
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
9821a50eaa
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
c5cbe43732
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
e6987524ab
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
cc7d1c8ef9
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
4fb467ee8a
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
cab0349701
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
429bdae1c4
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
b08c87cb47
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
slmnemo
|
7348af7fd5
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
5218865a7f
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
4da96c5791
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
141f2a40e4
|
UART updates and PMA fix
|
2022-07-22 14:49:03 -07:00 |
|
slmnemo
|
9cca567136
|
Added test comments to reference output
|
2022-07-22 12:35:59 -07:00 |
|
Daniel Torres
|
0e75142ef4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|