David Harris
7360be1234
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
13f1aa1ebf
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs
2024-06-26 22:15:18 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840
2024-06-26 22:00:29 -07:00
Ross Thompson
91c844ca45
Removed more *** from camline and csrc.
2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59
Moved the *** from trap to an issue.
2024-06-19 12:31:24 -07:00
Ross Thompson
ab1af0fabf
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2024-06-19 09:25:39 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
Rose Thompson
04744032d8
Updated more signal names to match book.
2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6
Signal name changes to match book.
2024-06-02 16:32:25 -05:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
3ea16c6057
Removed note about store stall being depricated
2024-04-17 03:34:11 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
Rose Thompson
0d8c251fa4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-06 15:35:34 -06:00
David Harris
e0eb91f795
Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places
2024-03-06 11:02:04 -08:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
dd33479056
Switched to ?: for gating per section 4.2.4.3
2024-03-06 04:59:58 -08:00
Rose Thompson
c093f53c9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
Cleaned up the cacheLRU.
2024-03-05 11:08:40 -06:00
David Harris
c77afcb7e6
Removed floprc with synchronous reset and synchornous clear
2024-02-19 22:28:55 -08:00
Rose Thompson
aa15a63d9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-31 13:12:32 -06:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
4c2ba2b0b4
Added StoreStall back to csrc.
2024-01-18 14:43:34 -06:00
David Harris
ed9fa07ba3
tests/coverage/tlbmisc.S
2024-01-15 07:16:11 -08:00
Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
2c2f692f3a
Moved forwarding logic into controller
2023-12-26 21:17:01 -08:00
David Harris
8eace30f49
Moved UnalignedPCNextF mux into IFU
2023-12-20 16:18:31 -08:00
David Harris
b0f34a6377
Made priority of misalignment depend on ZICCLSM_SUPPORTED and made StoreAmo take prioirty over load faults
2023-12-19 12:51:45 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
3f3c20a38f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-21 14:04:02 -08:00
David Harris
b5f79c44f9
Reset STIMECMP to 0 to agree with ImperasDV
2023-11-21 13:43:51 -08:00
Rose Thompson
386cf3eb56
Merge pull request #493 from stineje/main
...
marchid approved by RISC-V
2023-11-21 08:33:07 -08:00
James E. Stine
141cbd3f9f
Update marchid/mvendorid for CV-Wally
2023-11-21 09:23:02 -06:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd
Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
2023-10-30 07:06:34 -07:00
Rose Thompson
06b5a92eff
Updated comments about Interrupt and wfi.
2023-10-26 12:24:36 -05:00
Rose Thompson
3322ff915e
Cleaned up the implementation changes for wfi.
2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901
This version passes the regression test and solves issue #200 . wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034
Possible fix for wfi.
2023-10-24 18:08:33 -05:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
Ross Thompson
e02d3577ec
Fixed issue #412
...
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
7a092a2275
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
David Harris
c6631ef808
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
