David Harris aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator		2023-12-13 11:33:59 -08:00
..
csr.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
csrc.sv
csri.sv
csrm.sv	Update marchid/mvendorid for CV-Wally	2023-11-21 09:23:02 -06:00
csrs.sv	Reset STIMECMP to 0 to agree with ImperasDV	2023-11-21 13:43:51 -08:00
csrsr.sv
csru.sv
privdec.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
privileged.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
privmode.sv
privpiperegs.sv
trap.sv	Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator	2023-12-13 11:33:59 -08:00