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113 Commits

Author SHA1 Message Date
David Harris
fa98ae8c30 Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED 2024-08-08 05:27:35 -07:00
David Harris
0ab3f28991 Lint cleanup 2024-06-20 00:10:03 -07:00
Ross Thompson
24916d42e2 Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw. 2024-06-19 11:40:02 -07:00
Ross Thompson
77523c52c2 LSU no longer has ***. 2024-06-19 10:56:07 -07:00
Ross Thompson
5e5ca0809f Removed more *** from lsu and updated assertions for dtim. 2024-06-19 10:52:51 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
David Harris
cac67aae4f Lint cleanup 2024-06-18 05:58:54 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
Rose Thompson
84946919a4 Changed name CacheWriteData to WriteData. 2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99 Changed name of cache parameter NUMLINES to NUMSETS to better match book. 2024-05-28 17:55:43 -05:00
David Harris
77137f0f60 ZAAMO and ZALRSC implemented but not tested 2024-05-07 16:45:49 -07:00
David Harris
c0afb44ed4 Tied dangling signals to 0 for some configs to make VCS lint happy 2024-04-28 22:50:36 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
Rose Thompson
0d8c251fa4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-03-06 15:35:34 -06:00
Rose Thompson
2f94be5e79 Revert "Optimized the align logic for loads." 
This reverts commit 1fd678b433.
 2024-03-06 15:19:17 -06:00
Rose Thompson
57aab52dc2 Revert "Partially working optimized subwordwrite for misaligned." 
This reverts commit dac8fc16af.
 2024-03-06 15:17:57 -06:00
Rose Thompson
9668fdd868 Revert "Closer to getting subword write misaligned working." 
This reverts commit 6a9c2d8dc4.
 2024-03-06 15:16:43 -06:00
Rose Thompson
dce7de59a3 Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur." 
This reverts commit 3714b2bf4a.
 2024-03-06 15:16:37 -06:00
Rose Thompson
f752b5dd37 Revert "Beginning subword cleanup." 
This reverts commit 7e1ea1e6d9.
 2024-03-06 15:16:24 -06:00
Rose Thompson
a8024eee26 Revert "Updated subword misaligned." 
This reverts commit 69d31d50e2.
 2024-03-06 15:16:16 -06:00
Rose Thompson
e7ec2bedd4 Revert "Simplifications of subword code." 
This reverts commit a402883115.
 2024-03-06 15:15:51 -06:00
Rose Thompson
5447159cfd Revert "Cleanup." 
This reverts commit e84b7cc147.
 2024-03-06 15:15:26 -06:00
Rose Thompson
2ea0134329 Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned." 
This reverts commit cba3209e7f.
 2024-03-06 13:28:59 -06:00
Rose Thompson
068ffda5fb Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."" 
This reverts commit 8136b45ca7.
 2024-03-06 13:28:47 -06:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
Kevin Kim
9d73e5bd0d lsu supports quad enabled subwordreads 2024-03-05 17:07:39 -08:00
Rose Thompson
a22de45631 Removed unused storedelay from align. 2024-03-02 16:20:31 -06:00
Rose Thompson
8136b45ca7 Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned." 
This reverts commit cba3209e7f.
 2024-03-02 11:55:43 -06:00
Rose Thompson
cba3209e7f Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned. 2024-03-02 11:38:33 -06:00
Rose Thompson
ab750e150f Fixed lint errors for alignment. 2024-02-23 14:00:19 -06:00
Rose Thompson
e84b7cc147 Cleanup. 2024-02-23 13:00:21 -06:00
Rose Thompson
a402883115 Simplifications of subword code. 2024-02-23 09:41:59 -06:00
Rose Thompson
69d31d50e2 Updated subword misaligned. 2024-02-22 13:29:39 -06:00
Rose Thompson
7e1ea1e6d9 Beginning subword cleanup. 2024-02-22 09:37:16 -06:00
Rose Thompson
3714b2bf4a Non-ideal fix. Added new output from pma which indicates if the write shift should occur. 
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
 2024-02-22 09:14:43 -06:00
Rose Thompson
6a9c2d8dc4 Closer to getting subword write misaligned working. 2024-02-20 20:23:42 -06:00
Rose Thompson
dac8fc16af Partially working optimized subwordwrite for misaligned. 2024-02-19 12:26:29 -06:00
Rose Thompson
1fd678b433 Optimized the align logic for loads. 2024-02-14 12:14:19 -06:00
Rose Thompson
e900bb09db Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-02-01 12:12:05 -06:00
David Harris
1c62c5e433 Fixed logic to work with FLEN < XLEN 2024-01-31 20:24:16 -08:00
Rose Thompson
aa15a63d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-01-31 13:12:32 -06:00
David Harris
f37c7bb1f6 Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this 2024-01-30 06:27:18 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
81d006536a Lint passes with 32-bit no D$, but many regressions fail. 2024-01-18 09:48:44 -06:00
Rose Thompson
ff6bb3be0c Fixed another bug with virtual memory and no caches. 2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4 Fixed it so Virtual Memory work without a D$. 2024-01-18 09:18:17 -06:00
Rose Thompson
dfe5ef4427 Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185 Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit. 2024-01-15 17:36:01 -06:00
Rose Thompson
83df3dfe83 Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00