118 Commits

Author	SHA1	Message	Date
Jacob Pease	ebdf25a53b	Commented out references to old axi IP from wally.tcl.	2024-07-24 22:47:15 -05:00
Jacob Pease	2caf9e93be	Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.	2024-07-24 22:46:24 -05:00
Jacob Pease	7ecd1c7d5f	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
Rose Thompson	8123695831	Maded insert_debug_comment.sh compatible with cygwin.	2024-04-22 10:48:34 -05:00
Rose Thompson	3bed733301	Fixed fpga to work with the updated regression changes.	2024-04-22 10:42:01 -05:00
Rose Thompson	c1221e6608	Fixed insert_debug_comment.sh to work with the older version of bash.	2024-04-16 10:55:26 -05:00
Rose Thompson	cc7f433ce0	Update the fpga scripts to use the new derivative configs.	2024-01-31 13:19:28 -06:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
Rose Thompson	26cd22c388	Replaced fpga's verilog top with system verilog.	2023-12-15 13:42:52 -06:00
Rose Thompson	dab9d7ab3c	Replaced fpga top level verilog with system verilog.	2023-12-15 13:07:08 -06:00
Rose Thompson	34631c54d3	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
Jacob Pease	7e494f2d3b	Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.	2023-12-01 18:59:18 -06:00
Jacob Pease	71066cae12	Modified FPGA Makefile to override with relative path. FPGA boots now.	2023-11-30 17:51:15 -06:00
Jacob Pease	ff73f798ed	Replaced vivado-risc-v addins directory with new SDC repo.	2023-11-16 13:59:12 -06:00
Rose Thompson	d4bc9da085	Fixed another bug in the updated script changes.	2023-11-13 18:12:02 -06:00
Rose Thompson	f8b65f50b0	Fixed bugs in the updated fpga synthe script.	2023-11-13 18:10:22 -06:00
Rose Thompson	d5f0c15b90	Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.	2023-11-13 17:48:28 -06:00
Rose Thompson	6b7ff50a84	Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.	2023-11-13 16:44:02 -06:00
Ross Thompson	055e00b8ac	Pushed vcu118 to 71MHz.	2023-08-25 17:04:50 -05:00
Jacob Pease	2bf6207919	Added help option to the flash-sd script.	2023-08-22 13:37:33 -05:00
Ross Thompson	cab40e618f	Updateds to vcu118 constraints and device tree.	2023-08-02 16:51:32 -05:00
Ross Thompson	fb1c1a1832	Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.	2023-08-02 16:14:04 -05:00
Ross Thompson	c4ae856f92	Clean up vcu118 synth scripts.	2023-08-01 14:39:33 -05:00
Ross Thompson	06efd2cdde	Pushed performance of arty a7 to 23Mhz.	2023-07-31 14:13:09 -05:00
Jacob Pease	9d33e08dbb	Removed non-existent SDC dependency from VCU targets in FPGA Makefile.	2023-07-27 15:01:20 -05:00
Ross Thompson	b1f7a5768f	Removed all old references to the old flash card controller. ... Added git submodule for the flash card in addins. Replicated flash card top level for our changes into the fpga/src directory.	2023-07-24 15:45:57 -05:00
Ross Thompson	49b87d4550	Merge branch 'main' of github.com:ross144/cvw	2023-07-24 10:47:05 -05:00
Ross Thompson	065e5e98c9	Improved timing constraints for arty a7 to push clock speed to 20Mhz.	2023-07-24 10:46:49 -05:00
Ross Thompson	ab6ef5bb58	At least it simulates and gets through fpga elaboration.	2023-07-21 18:40:26 -05:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Jacob Pease	380d96b359	Working new boot process. Buildroot package for sdc.	2023-07-20 14:15:59 -05:00
Ross Thompson	2752e5de4c	Fixed a bunch of timing constraints for the arty a7 board.	2023-07-19 17:08:16 -05:00
Ross Thompson	b756b248b4	Wow. The newest version of Vivado does not like the enums as parameters. ... The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.	2023-07-18 15:07:10 -05:00
Ross Thompson	a8f11dcad0	FPGA updates.	2023-06-20 11:11:34 -05:00
Ross Thompson	af187d96ca	Updated fpga wave config.	2023-06-19 12:28:30 -05:00
Ross Thompson	1a23f1360f	Updated fpga wally wrapper to work with the ILA.	2023-06-19 12:15:48 -05:00
Ross Thompson	0423d7df82	I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.	2023-06-16 17:00:27 -05:00
Ross Thompson	443c568994	Vivado requires an intermediate wrapper file for parameterization.	2023-06-16 16:30:14 -05:00
Ross Thompson	c44d4321fb	FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.	2023-06-16 15:40:13 -05:00
Jacob Pease	40f81d5da6	The Vivado-RISC-V SDC works. Wally is now booting through it.	2023-05-26 15:42:33 -05:00
Ross Thompson	6907f0ccc1	FPGA makefile update.	2023-04-25 16:24:26 -05:00
Ross Thompson	f22e6d0e48	Updated fpga Makefile to work with both the Arty and VCU platforms.	2023-04-21 11:08:35 -05:00
Jacob Pease	2839f4f41a	AHB triggers write, but AXI side doesn't update.	2023-04-18 15:23:22 -05:00
Ross Thompson	3588c53e66	It's almost working.	2023-04-18 14:24:59 -05:00
Ross Thompson	deb0bfc24d	Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.	2023-04-17 20:05:59 -05:00
Ross Thompson	b0f0fb1da7	Adding in the ILA to the arty a7.	2023-04-17 14:54:10 -05:00
Ross Thompson	30d017c258	Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.	2023-04-17 12:16:31 -05:00
Ross Thompson	fe692dacce	Finally got the arty a7 to build.	2023-04-17 11:54:22 -05:00
Ross Thompson	4ad33d7acc	OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(	2023-04-17 11:10:19 -05:00
Ross Thompson	5591b447d6	Fixed more issues with arty a7 constarints.	2023-04-16 13:25:02 -05:00