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..
debug
bootrom.txt
insert_debug_comment.sh
Makefile
probe
wally.tcl
wave_config.wcfg
xlnx_ahblite_axi_bridge.tcl
xlnx_axi_clock_converter.tcl
xlnx_ddr3-artya7-mig.prj
xlnx_ddr3-ArtyA7.tcl
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl
xlnx_ddr4.tcl
xlnx_mmcm.tcl	OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(	2023-04-17 11:10:19 -05:00
xlnx_proc_sys_reset.tcl