Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,965 Commits 4 Branches 2 Tags 53 MiB
e70b28f7f6
Commit Graph

707 Commits

Author SHA1 Message Date
Ross Thompson
d716c25275 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
ad29e19a27 fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
529f48ed58 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
76302a8599 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
52562c9190 new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
b5454f3a55 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
d8ea12c6f4 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
David Harris
72e216d053 APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
5f5ad77d4a Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
c8ac05ba7b AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
ca95b46de5 Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
1a356312b2 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
abfd935e06 removed delay in ahblite 2022-07-05 04:59:28 +00:00
Katherine Parry
2fc795ca70 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
8ac722f693 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
0fa35acbc5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
89b319aa1b FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
8930cdcfbb some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
Katherine Parry
8f98f3bfab added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
0417a6a45b very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
Katherine Parry
a5fb60eb1a radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
adaee899bb radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
70a1bb8377 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
fa1623551c passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
6d6cc7bb48 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
43882d5878 modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a85a868b56 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
9eefba5b58 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
ff1fae74d8 division by zero added 2022-06-24 01:09:44 +00:00
Katherine Parry
ec2c446c7e forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
b16e55906a div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
749d405da8 lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
de71773d69 added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
bca8fe1694 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
David Harris
44216b3967 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
d969edeb99 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
Katherine Parry
d7a363aaa7 fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
1612daa294 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Madeleine Masser-Frye
6229779b97 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
3c08861479 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
c9cbf6082d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
0ffaec850b postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
154a1c80c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
84256924e7 cleanup, plots for paper 2022-06-15 18:28:36 +00:00
Katherine Parry
08b2481917 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
Katherine Parry
8e19331ad5 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
674c31ce59 fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
802bfd74fb Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
3c44b5842b Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
05a217c7e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
c5d2037a7f Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
a21d731834 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
9080e35e54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
09d72a33c5 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
9f4ca06f7f Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
a79737e95b Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
d6a1ee1141 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
31852fdb19 Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
0e10435fb6 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
032385aee3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
374dfd1fc2 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
slmnemo
5ac17eca1d Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
75dffe4dcc Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
a4c7d1d936 ? 2022-06-09 17:50:47 -07:00
slmnemo
c4bc608268 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
cc8acd947d Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c1a40a15dd New RAM for further testing 2022-06-09 23:50:43 +00:00
David Harris
5612ca7041 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
8ae57f075f Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
1605544bfc Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
88285c684c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a54837b102 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
655266a216 Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
a64e65e54c Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
dd33f2a009 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
be658d3933 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
571eb21f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
38382e3a11 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
slmnemo
85801e75db Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
90c5e5d319 Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
Katherine Parry
eb93bd46d7 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Madeleine Masser-Frye
2383ca4f53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
6c6a12cfd5 added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
5ae63f913a fixed compilation errors 2022-06-03 15:34:17 +00:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
ccda4c771e fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
David Harris
9065b684f8 Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
7cf5d481c0 Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
Katherine Parry
74b549ddc8 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
Katherine Parry
707067548f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
108f32e9df Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
slmnemo
56121b3587 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
2b80788235 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
c24f88c2e9 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
efe4b3e8fe Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
99da6537cc Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
79df271a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
31815422d2 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
Katherine Parry
cd7fe9af61 reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
559c0c278e added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
2935188035 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
d1ef3b8981 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
835a4e4606 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
f426850bc7 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
80315fedff fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4335895b21 Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
822866fd0a removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
d5c249bf71 unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
3c63db9554 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
b288f812ab moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
efb972c6d3 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bddc32ed21 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
efce3e4953 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
Katherine Parry
550c4d380c fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
ae460eccd4 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
slmnemo
80965f953c added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
95d64fe4ae idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
Katherine Parry
f4b9ade942 added fcvt.sv 2022-05-26 00:10:51 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
c8892f2847 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
7d1448d2ad added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
Ross Thompson
1dde9db2ce Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
99aa110615 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
ff8e158ec4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
0bcae85792 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
fcaf032a0d ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
Katherine Parry
6bc31f2e78 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
4a2538455d added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
Katherine Parry
bc4804d90a fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
b0881495a9 Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
b255f61521 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
710905b239 updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
cc0ab94ebc Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
mmasserfrye
1442afe4e2 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
0265d1988e adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
mmasserfrye
43cf4f35cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
24420dea6c added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00