707 Commits

Author	SHA1	Message	Date
David Harris	e70b28f7f6	FMA cleanup	2022-08-02 07:42:32 -07:00
David Harris	2b932c4b80	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-02 07:34:12 -07:00
David Harris	887e4c73fb	Moved InvA to sign block; simplified fmaexpadd coding	2022-08-02 07:34:09 -07:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
David Harris	06c4f18cd1	merged lza back into main	2022-08-01 19:45:21 -07:00
David Harris	8147f75399	Fixed fmaadd to work with new LZA	2022-08-01 19:40:55 -07:00
Ross Thompson	797d9e3610	Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.	2022-08-01 21:12:25 -05:00
Ross Thompson	3cd8404917	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Ross Thompson	3612db2d70	pulled swbbytemask out of subword write.	2022-08-01 20:48:45 -05:00
David Harris	7e4b04ff64	Parameterized fmalza	2022-08-01 16:18:02 -07:00
David Harris	94fa7a00e7	Completed LZA simplificaiton	2022-08-01 16:13:16 -07:00
David Harris	3b937b73fd	lza cleanup	2022-08-01 16:01:02 -07:00
David Harris	b614f165fb	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 15:47:58 -07:00
David Harris	91597bba87	lza cleanup	2022-08-01 15:47:03 -07:00
David Harris	f56b26ec40	lza cleanup	2022-08-01 15:43:48 -07:00
David Harris	c3e9719c99	lza cleanup	2022-08-01 15:40:12 -07:00
David Harris	d6b5e7a6ef	lza cleanup	2022-08-01 15:37:09 -07:00
Katherine Parry	8ff3a693af	regression passes fpu tests	2022-08-01 19:56:25 +00:00
Katherine Parry	9c68f85822	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-08-01 19:55:50 +00:00
David Harris	2869d67e50	more lza cleanup	2022-08-01 12:34:00 -07:00
David Harris	b34d2065c3	LZA cleanup	2022-08-01 12:30:42 -07:00
David Harris	99462049e7	LZA refactoring switched to Pp1, Gm1, Km1	2022-08-01 12:20:23 -07:00
David Harris	3c08aabcd3	LZA refactoring	2022-08-01 11:36:21 -07:00
Katherine Parry	eddf6e9ee1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-08-01 18:35:07 +00:00
David Harris	7f9b601467	fmalza edits to match textbook	2022-08-01 18:23:39 +00:00
David Harris	257107f908	Partitioned fma into separate files	2022-08-01 18:07:38 +00:00
Ross Thompson	1ee613ae6c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-31 12:48:51 -05:00
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
David Harris	93d7d7179e	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
Ross Thompson	40e7cda84a	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	cd68896637	Merged evict dirty clear with flush write back.	2022-07-24 00:22:43 -05:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Katherine Parry	655e2d3810	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	bfced6bfe8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
David Harris	d22587090b	Reset MSR on read	2022-07-22 04:29:27 +00:00
slmnemo	3d2c6683d8	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Katherine Parry	7950a675ea	added input enables and improved forwarding	2022-07-21 01:20:06 +00:00
Katherine Parry	a30d9c6bd8	turn off 2 word store durring non-fp instructions	2022-07-20 21:57:23 +00:00
Ross Thompson	1cad05fef9	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00