707 Commits

Author	SHA1	Message	Date
Ross Thompson	fffaf654e6	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	13dbf3cc0f	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
Ross Thompson	cb301a78ad	Fixed bug where last line of dcache was not written back to memory on dcache flush.	2022-01-04 21:55:48 -06:00
Ross Thompson	ecc7bf5237	Fixed dcache flush.	2022-01-04 18:40:58 -06:00
David Harris	d1a7416028	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00